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| 型號： | MCP4706A0T-E/MAY |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 61/86頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT NV EEP I2C 6DFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | EEPROM，I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.1W |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-VDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 6-DFN（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
| 其它名稱： | MCP4706A0T-E/MAYDKR |
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MCP4706/4716/4726
DS22272C-page 64
2011-2012 Microchip Technology Inc.
8.2
Power Supply Considerations
The power source should be as clean as possible. The
power supply to the device is also used for the DAC
voltage reference internally if the internal VDD is
selected as the resistor ladder’s reference voltage
(VREF1:VREF0 = 00 or 01).
Any noise induced on the VDD line can affect the DAC
performance. Typical applications will require a bypass
capacitor in order to filter out high-frequency noise on
the VDD line. The noise can be induced onto the power
supply’s traces or as a result of changes on the DAC
output. The bypass capacitor helps to minimize the
effect of these noise sources on signal integrity.
Figure 8-2 shows an example of using two bypass
capacitors (a 10 F tantalum capacitor and a 0.1 F
ceramic capacitor) in parallel on the VDD line. These
capacitors should be placed as close to the VDD pin as
possible (within 4 mm). If the application circuit has
separate digital and analog power supplies, the VDD
and VSS pins of the device should reside on the analog
plane.
FIGURE 8-2:
Example MCP47X6 Circuit
with SOT-23 package.
Analog
VDD
1
2
3
6
4
VDD
SDA
SCL
VSS
VOUT
5
R1 R2
To MCU
R1 and R2 are I2C pull-up resistors:
R1 and R2:
5k
Ω - 10 kΩ for f
SCL
= 100 kHz to 400 kHz
~700
Ω for f
SCL
= 3.4 MHz
C1:
0.1 F capacitor
Ceramic
C2:
10 F capacitor
Tantalum
C3:
~ 0.1 F
Optional to reduce noise
in VOUT pin.
C4:
0.1 F capacitor
Ceramic
C5:
10 F capacitor
Tantalum
C2
C1
MC
P47X6
C3
Optional
(a) Circuit when VDD is selected as reference
(Note: VDD is connected to the reference circuit internally.)
(b) Circuit when external reference is used.
Output
VREF
Analog
VDD
1
2
3
6
4
VDD
SDA
SCL
VSS
VOUT
5
R1 R2
To MCU
C2
C1
MCP47X6
C3
Optional
Output
VREF
C4
Optional
VREF
Note: Pin assignment is opposite in DFN-6 package.
C5
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