SERIAL INTERFACE (I2
參數(shù)資料
型號： MCP4661T-503E/ML
廠商： Microchip Technology
文件頁數(shù)： 42/92頁
文件大?。?/td> 0K
描述： IC DGTL POT 50K 256TAPS 16-QFN
標(biāo)準(zhǔn)包裝： 1
接片： 257
電阻（歐姆）： 50k
電路數(shù)： 2
溫度系數(shù)： 標(biāo)準(zhǔn)值 150 ppm/°C
存儲器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 16-QFN-EP（4x4）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 677 (CN2011-ZH PDF)
其它名稱： MCP4661T-503E/MLDKR
2008 Microchip Technology Inc.
DS22107A-page 47
MCP454X/456X/464X/466X
6.0
SERIAL INTERFACE (I2C)
The MCP45XX/46XX devices support the I2C serial
protocol. The MCP45XX/46XX I2C’s module operates
in Slave mode (does not generate the serial clock).
Figure 6-1 shows a typical I2C Interface connection. All
I2C interface signals are high-voltage tolerant.
The MCP45XX/46XX devices use the two-wire I2C
serial interface. This interface can operate in standard,
fast or High-Speed mode. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access and generates the
START and STOP conditions. The MCP45XX/46XX
device works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated. Communi-
cation is initiated by the master (microcontroller) which
sends the START bit, followed by the slave address
byte. The first byte transmitted is always the slave
address byte, which contains the device code, the
address bits, and the R/W bit.
Refer to the Phillips I2C document for more details of
the I2C specifications.
FIGURE 6-1:
Typical I2C Interface Block
Diagram.
6.1
Signal Descriptions
The I2C interface uses up to five pins (signals). These
are:
SDA (Serial Data)
SCL (Serial Clock)
A0 (Address 0 bit)
A1 (Address 1 bit)
A2 (Address 2 bit)
6.1.1
SERIAL DATA (SDA)
The Serial Data (SDA) signal is the data signal of the
device. The value on this pin is latched on the rising
edge of the SCL signal when the signal is an input.
With the exception of the START and STOP conditions,
the high or low state of the SDA pin can only change
when the clock signal on the SCL pin is low. During the
high period of the clock the SDA pin’s value (high or
low) must be stable. Changes in the SDA pin’s value
while the SCL pin is HIGH will be interpreted as a
START or a STOP condition.
6.1.2
SERIAL CLOCK (SCL)
The Serial Clock (SCL) signal is the clock signal of the
device. The rising edge of the SCL signal latches the
value on the SDA pin. The MCP45XX/46XX supports
three I2C interface clock modes:
Standard Mode: clock rates up to 100 kHz
Fast Mode: clock rates up to 400 kHz
High-Speed Mode (HS mode): clock rates up to
3.4 MHz
The MCP4XXX will not strech the clock signal (SCL)
since memory read acceses occur fast enough.
Depending on the clock rate mode, the interface will
display different characteristics.
6.1.3
THE ADDRESS BITS (A2:A1:A0)
There are up to three hardware pins used to specify the
device address. The number of adress pins is
determined by the part number.
Address 0 is multiplexed with the High Voltage
Command (HVC) function. So the state of A0 is latched
on the MCP4XXX’s POR/BOR event.
The state of the A2 and A1 pins should be static, that is
they should be tied high or tied low.
6.1.3.1
The High Voltage Command (HVC)
Signal
The High Voltage Command (HVC) signal is multi-
plexed with Address 0 (A0) and is used to indicate that
the command, or sequence of commands, are in the
High Voltage mode. High Voltage commands allow the
device’s WiperLock Technology and write protect
features to be enabled and disabled.
The HVC pin has an internal resistor connection to the
MCP45XX/46XXs internal VDD signal.
SCL
MCP4XXX
SDA
HVC/A0 (2)
I/O (1)
Host
Controller
Typical I2C Interface Connections
Note 1: If High voltage commands are desired,
some type of external circuitry needs to
be implemented.
2: These pins have internal pull-ups. If
faster rise times are required, then
external pull-ups should be added.
3: This pin could be tied high, low, or
connected to an I/O pin of the Host
Controller.
A1 (2, 3)
A2 (2, 3)
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