參數(shù)資料
型號(hào)： MCP4661T-103E/ST
廠(chǎng)商： Microchip Technology
文件頁(yè)數(shù)： 46/92頁(yè)
文件大?。?/td> 0K
描述： IC POT DGTL 10K DUAL 14-TSSOP
標(biāo)準(zhǔn)包裝： 2,500
接片： 257
電阻（歐姆）： 10k
電路數(shù)： 2
溫度系數(shù)： 標(biāo)準(zhǔn)值 150 ppm/°C
存儲(chǔ)器類(lèi)型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 帶卷 (TR)
MCP454X/456X/464X/466X
DS22107A-page 50
2008 Microchip Technology Inc.
6.2.4
ADDRESSING
The address byte is the first byte received following the
START condition from the master device. The address
contains four (or more) fixed bits and (up to) three user
defined hardware address bits (pins A2, A1, and A0).
These 7-bits address the desired I2C device. The
A7:A4 address bits are fixed to “0101” and the device
appends the value of following three address pins (A2,
A1, A0). Address pins that are not present on the
device are pulled up (a bit value of ‘1’).
Since there are up to three adress bits controlled by
hardware pins, there may be up to eight MCP4XXX
devices on the same I2C bus.
Figure 6-9 shows the slave address byte format, which
contains the seven address bits. There is also a read/
write bit. Table 6-2 shows the fixed address for device.
Hardware Address Pins
The hardware address bits
(A2, A1, and A0)
correspond to the logic level on the associated address
pins. This allows up to eight devices on the bus.
These pins have a weak pull-up enabled when the VDD
< VBOR. The weak pull-up utilizes the “smart” pull-up
technology and exhibits the same characteristics as the
High-voltage tolerant I/O structure.
The state of the A0 address pin is latch on POR/BOR.
This is required since High Voltage commands force
this pin (HVC/A0) to the VIHH level.
FIGURE 6-9:
Slave Address Bits in the
I2C Control Byte.
TABLE 6-2:
DEVICE SLAVE ADDRESSES
6.2.5
SLOPE CONTROL
The MCP45XX/46XX implements slope control on the
SDA output.
As the device transitions from HS mode to FS mode,
the slope control parmameter will change from the HS
specification to the FS specification.
For Fast (FS) and High-Speed (HS) modes, the device
has a spike suppression and a Schmidt trigger at SDA
and SCL inputs.
Device
Address
Comment
MCP45X1
‘0101 11’b + A0
Supports up to 2
devices. Note 1
MCP45X2
‘0101 1’b + A1:A0
Supports up to 4
devices. Note 1
MCP46X1
‘0101’b + A2:A1:A0 Supports up to 8
devices. Note 1
MCP46X2
‘0101 1’b + A1:A0
Supports up to 4
devices. Note 1
Note 1:
A0 is used for High-Voltage commands
and the value is latched at POR.
SA6A5 A4A3 A2 A1 A0 R/W
A/A
Start
bit
Slave Address
R/W bit
A bit (controlled by slave device)
R/W = 0 = write
R/W = 1 = read
A = 0 = Slave Device Acknowledges byte
A = 1 = Slave Device does not Acknowledge byte
“0” “1” “0” “1”
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