參數(shù)資料
型號(hào)： MCP4541T-502E/MS
廠商： Microchip Technology
文件頁(yè)數(shù)： 68/92頁(yè)
文件大小： 0K
描述： IC POT DGTL 5K SGL 8-MSOP
標(biāo)準(zhǔn)包裝： 2,500
接片： 129
電阻（歐姆）： 5k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 150 ppm/°C
存儲(chǔ)器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
MCP454X/456X/464X/466X
DS22107A-page 70
2008 Microchip Technology Inc.
8.5
Design Considerations
In the design of a system with the MCP4XXX devices,
the following considerations should be taken into
account:
8.5.1
POWER SUPPLY
CONSIDERATIONS
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-7 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 F. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 8-7:
Typical Microcontroller
Connections.
8.5.2
LAYOUT CONSIDERATIONS
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP4XXX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is capable of providing. Particularly harsh environ-
ments may require shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
8.5.3
RESISTOR TEMPCO
Characterization curves of the resistor temperature
coefficient
(Tempco)
are
shown
in
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end to end change is RAB resistance.
8.5.4
HIGH VOLTAGE TOLERANT PINS
High Voltage support (VIHH) on the Serial Interface pins
supports
user
configuration
of
the
Non-Volatile
EEPROM, Write Protect, and WiperLock feature.
VDD
VSS
MCP454X/456X/
4
6
4
X/
46
6X
0.1 F
PIC
Mic
roc
on
trol
le
r
0.1 F
SCL
SDA
W
B
A
Note:
In many applications, the High Voltage will
only be present at the manufacturing
stage so as to “l(fā)ock” the Non-Volatile
wiper value (after calibration) and the con-
tents of the EEPROM. This ensures that
the since High Voltage is not present
under normal operating conditions, that
these values can not be modified.
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