參數(shù)資料
型號： MCP4541T-104E/MS
廠商： Microchip Technology
文件頁數(shù)： 66/92頁
文件大小： 0K
描述： IC POT DGTL 100K SGL 8-MSOP
標(biāo)準(zhǔn)包裝： 2,500
接片： 129
電阻（歐姆）： 100k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 150 ppm/°C
存儲器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
2008 Microchip Technology Inc.
DS22107A-page 69
MCP454X/456X/464X/466X
8.4
Using the General Call Command
The use of the General Call Address Increment, Decre-
ment, or Write commands is analogous to the “Load”
feature (LDAC pin) on some DACs (such as the
MCP4921). This allows all the devices to “Update” the
output level “at the same time”.
For some applications, the ability to update the wiper
values “at the same time may be a requirement, since
they delay from writing to one wiper value and then the
next may cause application issues. A possible example
would be a “tuned” circuit that uses several MCP45XX/
46XX in rheostat configuration. As the system condition
changes (temperature, load, ...) these devices need to
be changed (incremented/decremented) to adjust for
the system change. These changes will either be in the
same direction or in opposite directions. With the
Potentiometer device the customer can either select
the PxB terminals (same direction) or the PxA
terminal(s) (opposite direction).
Figure 8-6 shows that the update of six devices takes
6*TI2CDLY time in “normal” operation, but only
1*TI2CDLY time in “General Call” operation.
Figure 8-5 shows two I2C bus configurations. In many
cases, the single I2C bus configuration will be
adequate. For applications that do not want all the
MCP45XX/46XX devices to do General Call support or
have a conflict with General Call commands, the
multiple I2C bus configuration would be used.
FIGURE 8-5:
Typical Application I2C Bus
Configurations.
FIGURE 8-6:
Example Comparison of “Normal Operation” vs. “General Call Operation” wiper
Updates.
Note:
The application system may need to
partition the I2C bus into multiple busses to
ensure that the MCP45XX/46XX General
Call commands do not conflict with the
General Call commands that the other I2C
devices may have defined. Also if only a
portion of the MCP45XX/46XX devices are
to require this synchronous operation,
then the devices that should not receive
these commands should be on the second
I2C bus.
Single I2C Bus Configuration
Host
Controller
Device 1
Device 3
Device n
Device 2
Device 4
Multiple I2C Bus Configuration
Host
Controller
Device 1a
Device 3a
Device na
Device 2a
Device 4a
Device 1b
Device 3b
Device nb
Device 2b
Device 4b
Bus b
Bus a
Device 1n
Device 3n
Device nn
Device 2n
Device 4n
Bus n
Normal Operation
General Call Operation
INC
POT01
INC
POT02
INC
POT03
INC
POT04
INC
POT05
INC
POT06
TI2CDLY
TI2CDLY = Time from one I
2C command completed to completing the next I2C command.
INC
POTs 01-06
INC
POTs 01-06
INC
POTs 01-06
INC
POTs 01-06
INC
POTs 01-06
INC
POTs 01-06
TI2CDLY
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