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參數資料
| 型號： | MCP4461T-503E/ST |
| 廠商： | Microchip Technology |
| 文件頁數： | 2/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 257TAPS 50K 20TSSOP |
| 標準包裝： | 2,500 |
| 接片： | 257 |
| 電阻（歐姆）： | 50k |
| 電路數： | 4 |
| 溫度系數： | 標準值 150 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
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MCP444X/446X
DS22265A-page 10
2010 Microchip Technology Inc.
Digital Inputs/Outputs (HVC/A0, A1, SDA, SCL, WP, RESET)
Schmitt Trigger
High Input
Threshold
VIH
0.45 VDD
—
V
All
Inputs
except
SDA
and
SCL
2.7V
≤ VDD ≤ 5.5V
(Allows 2.7V Digital VDD with
5V Analog VDD)
0.5 V
——
V
1.8V
≤ VDD ≤ 2.7V
0.7 VDD
—VMAX
V
SDA
and
SCL
100 kHz
0.7 VDD
—VMAX
V400 kHz
0.7 VDD
—VMAX
V1.7 MHz
0.7 VDD
—VMAX
V3.4 Mhz
Schmitt Trigger
Low Input
Threshold
VIL
—
0.2VDD
V
All inputs except SDA and SCL
-0.5
—
0.3VDD
V
SDA
and
SCL
100 kHz
-0.5
—
0.3VDD
V400 kHz
-0.5
—
0.3VDD
V1.7 MHz
-0.5
—
0.3VDD
V3.4 Mhz
Hysteresis of
Schmitt Trigger
Inputs
VHYS
—0.1VDD
—
V
All inputs except SDA and SCL
N.A.
—
V
SDA
and
SCL
100 kHz
VDD < 2.0V
N.A.
—
V
VDD ≥ 2.0V
0.1 VDD
——
V
400 kHz
VDD < 2.0V
0.05 VDD
——
V
VDD ≥ 2.0V
0.1 VDD
——
V
1.7 MHz
0.1 VDD
——
V
3.4 Mhz
High Voltage Input
Entry Voltage
VIHHEN
9.0
—
12.5
(Note 6)
V
Threshold for WiperLock Technology
High Voltage Input
Exit Voltage
VIHHEX
——
VDD +
0.8V
(Note 6)
V
High Voltage Limit
VMAX
——
12.5
(Note 6)
V
Pin can tolerate VMAX or less.
Output Low
Voltage (SDA)
VOL
VSS
—0.2VDD
VVDD < 2.0V, IOL = 1 mA,
VSS
—0.4
V
VDD ≥ 2.0V, IOL = 3 mA
AC/DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C
≤ TA ≤ +125°C (extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note 1:
Resistance is defined as the resistance between terminal A to terminal B.
2:
INL and DNL are measured at VW with VA = VDD and VB = VSS.
3:
MCP44X1
only.
4:
MCP44X2
only, includes VWZSE and VWFSE.
5:
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
6:
This specification by design.
7:
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8:
The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.
9:
POR/BOR is not rate dependent.
10:
Supply current is independent of current through the resistor network.
11:
When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
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