The I2C spec" />
參數(shù)資料
型號(hào)： MCP4461T-502E/ST
廠商： Microchip Technology
文件頁(yè)數(shù)： 54/100頁(yè)
文件大小： 0K
描述： IC DGTL POT 257TAPS 5K 20TSSOP
標(biāo)準(zhǔn)包裝： 2,500
接片： 257
電阻（歐姆）： 5k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 150 ppm/°C
存儲(chǔ)器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
2010 Microchip Technology Inc.
DS22265A-page 57
MCP444X/446X
6.2.6
HS MODE
The I2C specification requires that a high-speed mode
device must be ‘a(chǎn)ctivated’ to operate in high-speed
(3.4 Mbit/s) mode. This is done by the Master sending
a special address byte following the START bit. This
byte is referred to as the high-speed Master Mode
Code (HSMMC).
The MCP44XX device does not acknowledge this byte.
However, upon receiving this command, the device
switches to HS mode. The device can now
communicate at up to 3.4 Mbit/s on SDA and SCL
lines. The device will switch out of the HS mode on the
next STOP condition.
The master code is sent as follows:
1.
START condition (S)
2.
High-Speed Master Mode Code (0000 1XXX),
The XXX bits are unique to the high-speed (HS)
mode Master.
3.
No Acknowledge (A)
After switching to the High-Speed mode, the next
transferred byte is the I2C control byte, which specifies
the device to communicate with, and any number of
data bytes plus acknowledgements. The Master
Device can then either issue a Repeated Start bit to
address a different device (at High-Speed) or a Stop bit
to return to Fast/Standard bus speed. After the Stop bit,
any other Master Device (in a Multi-Master system) can
arbitrate for the I2C bus.
See Figure 6-10 for illustration of HS mode command
sequence.
For more information on the HS mode, or other I2C
modes, please refer to the Phillips I2C specification.
6.2.6.1
Slope Control
The slope control on the SDA output is different
between the Fast/Standard Speed and the High-Speed
clock modes of the interface.
6.2.6.2
Pulse Gobbler
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes < 10 ns during HS mode.
FIGURE 6-10:
HS Mode Sequence.
S
A
‘0 0 0 0 1 X X X’b
Sr
A
‘Slave Address’
A/A
“Data”
P
S = Start bit
Sr = Repeated Start bit
A = Acknowledge bit
A = Not Acknowledge bit
R/W = Read/Write bit
R/W
P = Stop bit (Stop condition terminates HS Mode)
F/S-mode
HS-mode
HS-mode continues
F/S-mode
Sr
A
‘Slave Address’ R/W
HS Select Byte
Control Byte
Command/Data Byte(s)
Control Byte
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