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| 型號： | MCP4241-104E/P |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 36/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT DL 100K 2CH 14-DIP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | WiperLock™ |
| 接片： | 129 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 150 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-PDIP |
| 包裝： | 管件 |
| 其它名稱： | MCP4241-104-E/P MCP4241-104-E/P-ND |
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2008 Microchip Technology Inc.
DS22059B-page 41
MCP414X/416X/424X/426X
6.1.4
SERIAL CLOCK (SCK)
(SPI FREQUENCY OF OPERATION)
The SPI interface is specified to operate up to 10 MHz.
The actual clock rate depends on the configuration of
the system and the serial command used. Table 6-1
shows the SCK frequency for different configurations.
TABLE 6-1:
SCK FREQUENCY
6.1.5
THE CS SIGNAL
The Chip Select (CS) signal is used to select the device
and frame a command sequence. To start a command,
or sequence of commands, the CS signal must
transition from the inactive state (VIH) to an active state
(VIL or VIHH).
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
If an error condition occurs for an SPI command, then
the Command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (VIL). To exit the
error condition, the user must take the CS pin to the VIH
level.
When the CS pin returns to the inactive state (VIH) the
SPI module resets (including the address pointer).
While the CS pin is in the inactive state (VIH), the serial
interface is ignored. This allows the Host Controller to
interface to other SPI devices using the same SDI,
SDO, and SCK signals.
The CS pin has an internal pull-up resistor. The resistor
is disabled when the voltage on the CS pin is at the VIL
level. This means that when the CS pin is not driven,
the internal pull-up resistor will pull this signal to the VIH
level.
When the CS pin is driven low (VIL), the
resistance becomes very large to reduce the device
current consumption.
The high voltage capability of the CS pin allows High
Voltage commands. High Voltage commands allow the
device’s WiperLock Technology and write protect
features to be enabled and disabled.
Memory Type Access
Command
Read
Write,
Increment,
Decrement
Non-Volatile
Memory
SDI, SDO
10 MHz
10 MHz (2, 3)
SDI/SDO
(1)
250 kHz (4) 10 MHz (2, 3)
Volatile
Memory
SDI, SDO
10 MHz
SDI/SDO
(1)
250 kHz (4)
10 MHz
Note 1:
MCP41X1 devices only
2:
Non-Volatile memory does not support
the Increment or Decrement command.
3:
After a Write command, the internal write
cycle must complete before the next SPI
command is received.
4:
This is the maximum clock frequency
without an external pull-up resistor.
Note:
There is a required delay after the CS pin
goes active to the 1st edge of the SCK pin.
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