參數(shù)資料
型號(hào)： MCP4231-104E/P
廠商： Microchip Technology
文件頁(yè)數(shù)： 24/59頁(yè)
文件大小： 0K
描述： IC DGTL POT DUAL 100K 2CH 14DIP
標(biāo)準(zhǔn)包裝： 30
接片： 129
電阻（歐姆）： 100k
電路數(shù)： 2
溫度系數(shù)： 標(biāo)準(zhǔn)值 150 ppm/°C
存儲(chǔ)器類型： 易失
接口： 4 線 SPI（芯片選擇）
電源電壓： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 通孔
封裝/外殼： 14-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 14-PDIP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 675 (CN2011-ZH PDF)
其它名稱： MCP4231-104-E/P
MCP4231-104-E/P-ND
Micrel, Inc.
KSZ8051MNL/RNL
July 2010
30
M9999-070910-1.0
Crossover Cable
A crossover cable connects a MDI device to another MDI device, or a MDI-X device to another MDI-X device. The
following figure depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 7. Typical Crossover Cable Connection
LinkMD
Cable Diagnostics
The LinkMD
function utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems,
such as open circuits, short circuits and impedance mismatches.
LinkMD
works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, and then analyzing the
shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the
approximate distance to the cabling fault. The LinkMD
function processes this TDR information and presents it as a
numerical value that can be translated to a cable distance.
LinkMD
is initiated by accessing register 1Dh, the LinkMD Control/Status Register, in conjunction with register 1Fh, the
PHY Control 2 Register. The latter register is used to disable auto MDI/MDI-X and to select either MDI or MDI-X as the
cable differential pair for testing.
NAND Tree Support
The KSZ8051MNL/RNL provides parametric NAND tree support for fault detection between chip I/Os and board. The
NAND tree is a chain of nested NAND gates in which each KSZ8051MNL/RNL digital I/O (NAND tree input) pin is an input
to one NAND gate along the chain. At the end of the chain, the CRS/CONFIG1 pin provides the output for the nested
NAND gates.
The NAND tree test process includes:
Enabling NAND tree mode
Pulling all NAND tree input pins high
Driving low each NAND tree input pin sequentially per the NAND tree pin order
Checking the NAND tree output to ensure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
The following tables list the NAND tree pin order.
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