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| 型號： | MCP4162-104E/SN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 25/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL SNGL 100K RHEO 8SOIC |
| 標準包裝： | 100 |
| 系列： | WiperLock™ |
| 接片： | 257 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 150 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設(shè)備封裝： | 8-SOICN |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 675 (CN2011-ZH PDF) |
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2008 Microchip Technology Inc.
DS22059B-page 31
MCP414X/416X/424X/426X
4.2.2.1
Status (STATUS) Register
This register contains 5 status bits. These bits show the
state of the WiperLock bits, the Shutdown bit the Write
Protect bit, and if an EEPROM write cycle is active. The
STATUS register can be accessed via the READ
commands. Register 4-1 describes each STATUS
register bit.
The STATUS register is placed at Address 05h.
REGISTER 4-1:
STATUS REGISTER
R-1
R-0
R-x
D8:D5
EEWA
WL1 (1)
WL0 (1)
SHDN
WP (1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 8-5
D8:D5:
Reserved. Forced to “1”
bit 4
EEWA:
EEPROM Write Active Status bit
This bit indicates if the EEPROM Write Cycle is occurring.
1
= An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory
locations are allowed (addresses 00h, 01h, 04h, and 05h)
0
= An EEPROM Write cycle is NOT currently occurring
bit 3
WL1:
WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 “WiperLock Technology”
for further information)
WiperLock (WL) prevents the Volatile and Non-Volatile Wiper 1 addresses and the TCON register bits
R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are required to enable and
disable WiperLock Technology.
1
= Wiper and TCON register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are
“Locked” (Write Protected)
0
= Wiper and TCON of Resistor Network 1 (Pot 1) can be modified
Note:
The WL1 bit always reflects the result of the last programming cycle to the non-volatile WL1
bit. After a POR or BOR event, the WL1 bit is loaded with the non-volatile WL1 bit value.
bit 2
WL0:
WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 “WiperLock Technology”
for further information)
The WiperLock Technology bits (WLx) prevents the Volatile and Non-Volatile Wiper 0 addresses and the
TCON register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are
required to enable and disable WiperLock Technology.
1
= Wiper and TCON register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are
“Locked” (Write Protected)
0
= Wiper and TCON of Resistor Network 0 (Pot 0) can be modified
Note:
The WL0 bit always reflects the result of the last programming cycle to the non-volatile WL0
bit. After a POR or BOR event, the WL0 bit is loaded with the non-volatile WL0 bit value.
bit 1
SHDN:
Hardware Shutdown pin Status bit (Refer to Section 5.4 “Shutdown” for further information)
This bit indicates if the Hardware shutdown pin (SHDN) is low. A hardware shutdown disconnects the
Terminal A and forces the wiper (Terminal W) to Terminal B (see Figure 5-2). While the device is in
Hardware Shutdown (the SHDN pin is low) the serial interface is operational so the STATUS register
may be read.
1
= MCP4XXX is in the Hardware Shutdown state
0
= MCP4XXX is NOT in the Hardware Shutdown state
Note 1:
Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is
Not directly written, but reflects the system state (for this feature).
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