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參數(shù)資料
| 型號： | MCP4131T-103E/SN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 26/59頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL SNGL 10K SPI 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 接片： | 129 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 150 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 3 線 SPI（芯片選擇） |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
KSZ8051MNL/RNL
July 2010
32
M9999-070910-1.0
NAND Tree I/O Testing
The following procedure can be used to check for faults on the KSZ8051MNL/RNL digital I/O pin connections to the
board:
1. Enable NAND tree mode by either hardware pin strapping (NAND_Tree#, pin 21) or software (register 16h, bit 5).
2. Use board logic to drive all KSZ8051MNL/RNL NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, per KSZ8051MNL/RNL NAND Tree pin order, as follow:
a. Toggle the first pin (MDIO) from high to low, and verify the CRS/CONFIG1 pin switch from low to high to
indicate that the first pin is connected properly.
b. Leave the first pin (MDIO) low.
c. Toggle the second pin (MDC) from high to low, and verify the CRS/CONFIG1 pin switch from high to low
to indicate that the second pin is connected properly.
d. Leave the first pin (MDIO) and the second pin (MDC) low.
e. Toggle the third pin from high to low, and verify the CRS/CONFIG1 pin switch from low to high to indicate
that the third pin is connected properly.
f.
Continue with this sequence until all KSZ8051MNL/RNL NAND tree input pins have been toggled.
Each KSZ8051MNL/RNL NAND tree input pin must cause the CRS/CONFIG1 output pin to toggle high-to-low or low-to-
high to indicate a good connection. If the CRS/CONFIG1 pin fails to toggle when the KSZ8051MNL/RNL input pin toggles
from high to low, the input pin has a fault.
Power Management
The KSZ8051MNL/RNL offers the following power management modes:
Power Saving Mode
Power Saving Mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by
writing a one to register 1Fh, bit 10, and is in effect when auto-negotiation mode is enabled and cable is disconnected (no
link).
In this mode, the KSZ8051MNL/RNL shuts down all transceiver blocks, except for transmitter, energy detect and PLL
circuits.
By default, Power Saving Mode is disabled after power-up.
Energy Detect Power Down Mode
Energy Detect Power Down Mode is used to further reduce the transceiver power consumption when the cable is un-
plugged. It is enabled by writing a zero to register 18h, bit 11, and is in effect when auto-negotiation mode is enabled and
cable is disconnected (no link).
In this mode, the KSZ8051MNL/RNL shuts down all transceiver blocks, except for transmitter and energy detect circuits.
Further power consumption is achieved by extending the time interval in between transmissions of link pulses to check for
the presence of a link partner. The periodic transmission of link pulses is needed to ensure two link partners in the same
low power state and with auto MDI/MDI-X disabled can wake up when the cable is connected between them.
By default, Energy Detect Power Down Mode is disabled after power-up.
Power Down Mode
Power Down Mode is used to power down the KSZ8051MNL/RNL device when it is not in use after power-up. It is
enabled by writing a one to register 0h, bit 11.
In this mode, the KSZ8051MNL/RNL disables all internal functions, except for the MII management interface. The
KSZ8051MNL/RNL exits (disables) Power Down Mode after register 0h, bit 11 is set back to zero.
Slow Oscillator Mode
Slow Oscillator Mode is used to disconnect the input reference crystal/clock on XI (pin 9) and select the on-chip slow
oscillator when the KSZ8051MNL/RNL device is not in use after power-up. It is enabled by writing a one to register 11h,
bit 5.
Slow Oscillator Mode works in conjunction with Power Down Mode to put the KSZ8051MNL/RNL device in the lowest
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