FIGURE 2-25: Potentiometer Divider Non- L" />
參數(shù)資料
型號: MCP41100T-I/SN
廠商: Microchip Technology
文件頁數(shù): 3/28頁
文件大?。?/td> 0K
描述: IC POT DIGITL 100K 1CH SPI 8SOIC
標準包裝: 3,300
接片: 256
電阻(歐姆): 100k
電路數(shù): 1
溫度系數(shù): 標準值 800 ppm/°C
存儲器類型: 易失
接口: 3 線串行(芯片選擇)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOICN
包裝: 帶卷 (TR)
2003 Microchip Technology Inc.
DS11195C-page 11
MCP41XXX/42XXX
2.1
Parametric Test Circuits
FIGURE 2-25:
Potentiometer Divider Non-
Linearity Error Test Circuit (DNL, INL).
FIGURE 2-26:
Resistor Position Non-
Linearity Error Test Circuit (Rheostat operation
DNL, INL).
FIGURE 2-27:
Wiper Resistance Test
Circuit.
FIGURE 2-28:
Power Supply Sensitivity
Test Circuit (PSS, PSRR).
FIGURE 2-29:
Gain vs. Frequency Test
Circuit.
FIGURE 2-30:
Capacitance Test Circuit.
V+
A
B
W
VMEAS*
V+ = VDD
1LSB = V+/256
DUT
*Assume infinite input impedance
+
-
A
B
W
DUT
IW
*Assume infinite input impedance
VMEAS*
No Connection
+
-
B
DUT
W
+
-
ISW
Rsw = 0.1V
Isw
Code = 00h
0.1V
VSS = 0 to VDD
A
V+
A
B
W
DUT
VA
V+ = VDD ± 10%
PSRR (dB) = 20LOG
VMEAS
)
(
PSS (%/%) =
VDD
VMEAS
VDD
*Assume infinite input impedance
VMEAS*
VDD
+
-
VIN
-
+
+5V
VOUT
2.5V DC
OFFSET
GND
A
B
DUT
W
~
VIN
-
+
+5V
VOUT
MCP601
2.5V DC
Offset
A
B
DUT
~
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