參數(shù)資料
型號(hào)： MCP3550-50E/MS
廠商： Microchip Technology
文件頁(yè)數(shù)： 8/36頁(yè)
文件大?。?/td> 0K
描述： IC ADC 22BIT 2.7V 1CH 8MSOP
產(chǎn)品培訓(xùn)模塊： MCP3901 Analog Front End
標(biāo)準(zhǔn)包裝： 100
位數(shù)： 22
采樣率（每秒）： 12.5
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，單極
產(chǎn)品目錄頁(yè)面： 672 (CN2011-ZH PDF)
配用： MCP355XDV-MS1-ND - BOARD DEV SENSOR APP MCP355X
MCP355XDM-TAS-ND - BOARD DEMO TINY APP SNSR MCP355X
MCP3550/1/3
DS21950E-page 16
2009 Microchip Technology Inc.
4.1
MCP3550/1/3 Delta-Sigma
Modulator with Internal Offset and
Gain Calibration
The converter core of the MCP3550/1/3 devices is a
third-order delta-sigma modulator with automatic gain
and offset error calibrations. The modulator uses a 1-bit
DAC structure. The delta-sigma modulator processes
the sampled charges through switched capacitor
structures controlled by a very low drift oscillator for
reduced clock jitter.
During the conversion process, the modulator outputs
a bit stream with the bit frequency equivalent to the
fOSC/4 (see Table 4-1). The high oversampling
implemented in the modulator ensures very high
resolution and high averaging factor to achieve low-
noise specifications. The bit stream output of the
modulator is then processed by the digital decimation
filter in order to provide a 22-bit output code at a data
rate of 12.5 Hz for the MCP3550-50, 15 Hz for the
MCP3550-60, 13.75 Hz for the MCP3551 and 60 Hz
for the MCP3553. Since the oversampling ratio is lower
with the MCP3553 device, a much higher output data
rate is achieved while still achieving 20 bits No Missing
Codes (NMC) and 20.6 ENOB.
A self-calibration of offset and gain occurs at the onset
of every conversion. The conversion data available at
the output of the device is always calibrated for offset
and gain through this process. This offset and gain
auto-calibration is performed internally and has no
impact on the speed of the converter since the offset
and gain errors are calibrated in real-time during the
conversion. The real-time offset and gain calibration
schemes do not affect the conversion process.
4.2
Digital Filter
The MCP3550/1/3 devices include a digital decimation
filter, which is a fourth-order modified SINC filter. This
filter averages the incoming bit stream from the
modulator and outputs a 22-bit conversion word in
binary two's complement. When all bits have been
processed by the filter, the output code is ready for SPI
communication, the RDY flag is set on the SDO/RDY
pin and all the internal registers are reset in order to
process the next conversion.
Like the commonly used SINC filter, the modified SINC
filter in the MCP3550/1/3 family has the main notch
frequency located at fS/(OSR*L), where fS is the bit
stream sample frequency. OSR is the Oversampling
Ratio and L is the order of the filter.
The MCP3550-50 device has the main filter notch
located at 50 Hz. For the MCP3550-60 device, the
notch is located at 60 Hz. The MCP3551 device has its
notch located at 55 Hz, and for the MCP3553 device,
the main notch is located at 240 Hz, with an OSR of
128. (see Table 4-1 for rejection performance).
The digital decimation SINC filter has been modified in
order to offer staggered zeros in its transfer function.
This modification is intended to widen the main notch in
order to be less sensitive to oscillator deviation or line-
frequency drift. The MCP3551 filter has staggered
zeros spread in order to reject both 50 Hz and 60 Hz
line frequencies simultaneously (see Figure 4-2).
TABLE 4-1:
DATA RATE, OUTPUT NOISE AND DIGITAL FILTER SPECIFICATIONS BY DEVICE
Device
Output Data
Rate (tCONV)
Output
Noise
(VRMS)
Primary
Notch
(Hz)
Sample
Frequency
(fS)
Internal
Clock
fOSC
50/60 Hz Rejection
MCP3550-50
80.00 ms
2.5
50
25600 Hz
102.4 kHz
-120 dB min. at
50 Hz
MCP3550-60
66.67 ms
2.5
60
30720 Hz
122.88 kHz
-120 dB min. at
60 Hz
MCP3551
72.73 ms
2.5
55
28160 Hz
112.64 kHz
-82 dB min. from
48 Hz to 63 Hz. -
82 dB at 50 Hz and
-88 dB at 60 Hz
MCP3553
16.67 ms
6
240
30720 Hz
122.88 kHz
Not Applicable
Note:
For the first conversion after exiting Shutdown, tCONV must include an additional 144 fOSC periods before
the conversion is complete and the RDY (Ready) flag appears on SDO/RDY.
相關(guān)PDF資料
PDF描述
MCP3551-E/MS IC ADC 22BIT 2.7V 1CH SPI 8MSOP
MCP3553-E/MS IC ADC 22BIT 2.7V 1CH SPI 8MSOP
TLC0834IN IC 8BIT 20KSPS ADC SER OUT14-DIP
MCP3424-E/ST IC ADC 18BIT 3.75SPS 4CH 14TSSOP
MCP3553-E/SN IC ADC 22BIT 2.7V 1CH SPI 8SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCP3550-50E-SN 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Low-Power, Single-Channel 22-Bit Delta-Sigma ADCs
MCP3550-50T-E/MS 制造商:Microchip Technology Inc 功能描述:22-BIT DELTA-SIGMA ADC, SINGLE - Tape and Reel
MCP3550-50T-E/SN 制造商:Microchip Technology Inc 功能描述:22-BIT DELTA-SIGMA ADC, SINGLE - Tape and Reel
MCP3550-60 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Low-Power, Single-Channel 22-Bit Delta-Sigma ADCs
MCP3550-60E/MS 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 22-bit ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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