參數(shù)資料
型號(hào)： MCP3304-CI/SL
廠商： Microchip Technology
文件頁(yè)數(shù)： 10/48頁(yè)
文件大小： 0K
描述： IC ADC 13BIT 2.7V 4CH SPI 16SOIC
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 13
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 管件
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；4 個(gè)差分，單極
產(chǎn)品目錄頁(yè)面： 672 (CN2011-ZH PDF)
其它名稱： MCP3304CI/SL
MCP3302/04
DS21697F-page 18
2011 Microchip Technology Inc.
FIGURE 5-3:
Analog Input Model.
5.2.1
MAINTAINING MINIMUM CLOCK
SPEED
When the MCP3302/04 initiates, charge is stored on
the sample capacitor. When the sample period is
complete, the device converts one bit for each clock
that is received. It is important for the user to note that
a slow clock rate will allow charge to bleed off the
sample capacitor while the conversion is taking place.
For the MCP330X devices, the recommended mini-
mum clock speed during the conversion cycle (TCONV)
is 105 kHz. Failure to meet this criteria may induce
linearity errors into the conversion outside the rated
specifications. It should be noted that during the entire
conversion cycle, the A/D converter does not have
requirements for clock speed or duty cycle, as long as
all timing specifications are met.
5.3
Biasing Solutions
For pseudo-differential bipolar operation, the biasing
circuit shown in Figure 5-4 shows a single-ended input
AC coupled to the converter. This configuration will give
a digital output range of -4096 to +4095. With the 2.5V
reference, the LSB size equal to 610 V.
Although the ADC is not production tested with a 2.5V
reference as shown, linearity will not change more than
0.1 LSB. See Figure 2-2 and Figure 2-6 for INL and
DNL errors versus V
REF at V
DD = 5V. A trade-off exists
between the high-pass corner and the acquisition time.
The value of C will need to be quite large in order to
bring down the high-pass corner. The value of R needs
to be 1 k, or less, since higher input impedances
require additional acquisition time.
Using the values in Figure 5-4, we have a 100 Hz cor-
ner frequency. See Figure 5-2 for relation between
input impedance and acquisition time.
FIGURE 5-4:
Pseudo-differential biasing
circuit for bipolar operation.
CPIN
VA
RS
CHx
7pF
VT = 0.6V
ILEAKAGE
Sampling
Switch
SS
RSS = 1 k
CSAMPLE
= DAC capacitance
VSS
VDD
= 25 pF
±1 nA
Legend
VA = signal source
RS = source impedance
CHx = input channel pad
CPIN = input pin capacitance
VT = threshold voltage
ILEAKAGE = leakage current at the pindue to various junctions
SS = sampling switch
RSS = sampling switch resistor
CSAMPLE = sample/hold capacitance
VDD = 5V
0.1 F
IN+
IN-
VREF
MCP330X
1F
MCP1525
VIN
VOUT
0.1 F
1k
10 F
VIN
R
C
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