參數(shù)資料
型號(hào)： MCP3204-CI/P
廠商： Microchip Technology
文件頁數(shù)： 15/40頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 2.7V 4CH SPI 14-DIP
標(biāo)準(zhǔn)包裝： 30
位數(shù)： 12
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 14-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 14-PDIP
包裝： 管件
輸入數(shù)目和類型： 4 個(gè)單端，單極；2 個(gè)偽差分，單極
產(chǎn)品目錄頁面： 672 (CN2011-ZH PDF)
MCP3204/3208
DS21298E-page 22
2008 Microchip Technology Inc.
FIGURE 6-2:
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
6.2
Maintaining Minimum Clock Speed
When the MCP3204/3208 initiates the sample period,
charge is stored on the sample capacitor. When the
sample period is complete, the device converts one bit
for each clock that is received. It is important for the
user to note that a slow clock rate will allow charge to
bleed off the sample capacitor while the conversion is
taking place. At 85°C (worst case condition), the part
will maintain proper charge on the sample capacitor for
at least 1.2 ms after the sample period has ended. This
means that the time between the end of the sample
period and the time that all 12 data bits have been
clocked out must not exceed 1.2 ms (effective clock
frequency of 10 kHz). Failure to meet this criterion may
introduce linearity errors into the conversion outside
the rated specifications. It should be noted that during
the entire conversion cycle, the A/D converter does not
require a constant clock speed or duty cycle, as long as
all timing specifications are met.
6.3
Buffering/Filtering the Analog
Inputs
If the signal source for the A/D converter is not a low
impedance source, it will have to be buffered or inaccu-
rate conversion results may occur (see Figure 4-2). It is
also recommended that a filter be used to eliminate any
signals that may be aliased back into the conversion
results, as is illustrated in Figure 6-3, where an op amp
is used to drive the analog input of the MCP3204/3208.
This amplifier provides a low impedance source for the
converter input, and a low pass filter, which eliminates
unwanted high frequency noise.
Low-pass (anti-aliasing) filters can be designed using
Microchip’s free interactive FilterLab software. Filter-
Lab will calculate capacitor and resistor values, as well
as determine the number of poles that are required for
the application. For more information on filtering
signals, see AN699, “Anti-Aliasing Analog Filters for
Data Acquisition Systems”
.
12
3
4
5
6
7
8
9
10 11 12 13 14 15
16
CS
SCLK
DIN
X = “Don’t Care” Bits
17 18 19 20 21 22 23 24
DOUT
DO
Don’t Care
NULL
BIT B11 B10 B9
B8
B6 B5 B4 B3 B2 B1 B0
HI-Z
000
00
1
XX
XXX
DO
SGL/
DIFF
XX
XXX
B7 B6 B5 B4 B3 B2 B1 B0
B11 B10 B9 B8
0
????
???
?
??
?
MCU latches data from A/D converter
on rising edges of SCLK
Data is clocked out of A/D
converter on falling edges
D1
D2
SGL/
DIFF
Start
Bit
(Null)
D1
D2
Start
MCU Transmitted Data
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
edge of clock)
B7
X
Data stored into MCU receive
register after transmission of first
8 bits
Data stored into MCU receive
register after transmission of
second 8 bits
Data stored into MCU receive
register after transmission of last
8 bits
DO
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