參數(shù)資料
型號： MCP25050-I/SL
廠商： Microchip Technology
文件頁數(shù)： 37/66頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER CAN 8B 14SOIC
標準包裝： 57
接口： CAN
輸入/輸出數(shù)： 8
中斷輸出： 無
頻率 - 時鐘： 4MHz
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
供應商設備封裝： 14-SOIC
包裝： 管件
包括： ADC，存儲器，PWM
產(chǎn)品目錄頁面： 685 (CN2011-ZH PDF)
其它名稱： MCP25050I/SL
MCP2502X/5X
DS21664D-page 42
2007 Microchip Technology Inc.
7.3.2
CONVERSION-ON-REQUEST
MODE
If the Conversion-on-request mode is selected, the
device performs an A/D conversion only after receiving
a Read A/D Registers or Read Register Receive
message (IRM). In the case of the Read A/D Registers
command, all of the GPIO pins that have been
configured as analog input channels will have an A/D
conversion done before the data frame is sent. When a
Read Register Receive message is initiated (extended
message format only), the A/D conversion is performed
when the MSB of the analog channel is requested, with
the MSB result being transferred. A subsequent read of
the LSB will transmit the value latched when the MSB
was requested (it is recommended that the Read A/D
Registers receive message is used to obtain complete
analog channel values in one message).
7.4
A/D Threshold Detection
Once an A/D auto-conversion has been completed, the
A/D channel result(s) can be compared to a value
stored in the associated A/D channel comparator
registers.
If the value in the analog channel result registers (i.e.,
AN0L and AN10H registers for analog channel 0) is
lower or higher than the value in the A/D comparator
registers (as specified by a corresponding polarity bit),
a transmit-on-change message will be sent (TXID2).
The
threshold-detection
function
for
all
analog
channels is bit-selectable.
If the A/D channel has been configured for transmit-on-
change mode, the MCP2505 will send a transmit
message with the appropriate data. It is possible that
more than one A/D channel has a change-of-state
condition. This does not pose a problem since all
analog channel data is provided in the transmit
message.
REGISTER 7-1:
A/D MODULE RESULT REGISTER MSB (ADRESNH)
REGISTER 7-2:
A/D MODULE RESULT REGISTER LSB (ADRESNL)
R-x
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
bit 7
bit 0
bit 7-0
AD9:AD2: Most Significant A/D Result bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
R-x
U-0
AD1
AD0
—
bit 7
bit 0
bit 7-6
AD1:AD0: Least significant A/D Result bits
bit 5-0
Unimplemented: Reads as ‘0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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