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| 型號： | MCP25025T-I/SL |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 43/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER CAN 8B 14SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,600 |
| 接口： | 1 線，CAN |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 無 |
| 頻率 - 時鐘： | 4MHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
| 包括： | 存儲器，PWM |
| 其它名稱： | MCP25025TI/SL |
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MCP2502X/5X
DS21664D-page 48
2007 Microchip Technology Inc.
REGISTER 8-1:
CONFIGURATION REGISTER
8.4
Reset
The MCP2502X/5X differentiates between two kinds of
reset:
Power-on Reset (POR)
External RST reset
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a reset
state on Power-on Reset (POR), on RST and on RST
during SLEEP. They are not affected by a wake-up from
SLEEP, which is viewed as the resumption of normal
operation. A simplified block diagram of the on-chip
reset circuit is shown in Figure 8-3. The MCP2502X/5X
has a RST noise filter in the RST reset path. The filter
will detect and ignore small pulses.
8.4.1
POWER-ON RESET
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V to 2.1V). If the
RST input on the GP7 pin is selected, the RST pin may
be tied through a series resistor to VDD, eliminating the
need for external RC components usually required for
a Power-on Reset. A maximum rise time for VDD is
specified in Section 9.0 “Electrical Characteristics”
of this document.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure
proper operation. For additional information, refer to
AN607, “Power-up Troubleshooting”, DS00607).
U-0
R/W-x
—
—R
R
bit 13
bit 8
R/W-x
R/W
R
RSTEN
FOSC1
FOSC0
bit 7
bit 0
bit 13-11
Unimplemented: Read as '0'
bit 10-3
Reserved: do not attempt to modify
bit 2
RSTEN: Enable RST input on GP7
1
=RST input Enabled
0
=RST input Disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11
= HS oscillator
10
= Reserved for Test (EC oscillator)
01
= XT oscillator
00
= LP oscillator
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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