參數(shù)資料
型號(hào)： MCP25020-E/SL
廠商： Microchip Technology
文件頁(yè)數(shù)： 66/66頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER CAN 8B 14SOIC
標(biāo)準(zhǔn)包裝： 57
接口： CAN
輸入/輸出數(shù)： 8
中斷輸出： 無(wú)
頻率 - 時(shí)鐘： 25MHz
電源電壓： 4.5 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 14-SOIC
包裝： 管件
包括： 存儲(chǔ)器，PWM
配用： MCP2515DM-PCTL-ND - BOARD DEMO FOR MCP2515
其它名稱(chēng)： MCP25020E/SL
2007 Microchip Technology Inc.
DS21664D-page 9
MCP2502X/5X
As a result of resynchronization, PS1 may be
lengthened or PS2 may be shortened. The amount of
lengthening or shortening of the phase buffer segments
has an upper-bound given by the SJW. The SJW is
programmable between 1 TQ and 4 TQ. The value of
the SJW will be added to PS1 (or subtracted from PS2)
depending on the phase error (e) of the edge in relation
to the receiver’s SyncSeg. The phase error is defined
as follows:
e = 0 if the edge lies within SYNCESEG
- No resynchronization is required.
e > 0 if the edge lies before the sample point
- PS1 will be lengthened by the amount of the
SJW.
e < 0 if the edge lies after the sample point of the
previous bit and before the SyncSeg of the
current bit
- PS2 will be shortened by the amount of the
SJW.
2.4.6
CONFIGURATION REGISTERS
There are three registers (in the configuration register
module) associated with the CAN bit timing logic that
controls the bit timing for the CAN bus interface.
2.4.6.1
CNF1
The BRP<5:0> bits control the baud rate prescaler.
These bits set the length of TQ relative to the OSC1
input frequency, with the minimum length of TQ being
2TOSC in length (when BRP<5:0> are set to 000000).
The SJW<1:0> bits select the synchronization jump
width in terms of number of TQ’s.
2.4.6.2
CNF2
The PRSEG<2:0> bits set the length (in TQ’s) of the
propagation segment. The PS1<2:0> bits set the length
(in TQ’s) of phase segment 1. The SAM bit controls how
many times the RXCAN pin is sampled. Setting this bit
to a ‘1’ causes the bus to be sampled three times.
Twice at TQ/2 before the sample point and once at the
normal sample point (which is at the end of PS1). The
value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘0’, the RXCAN pin is sampled only once at the
sample point. The BTLMODE bit controls how the
length of PS2 is determined. If this bit is set to a ‘1’, the
length of PS2 is determined by the PS2<2:0> bits of
CNF3. If the BTLMODE bit is set to a ‘0’ then the length
of PS2 is the greater of PS1 and the information
processing time (which is fixed at 2 TQ for the
MCP2502X/5X).
2.4.6.3
CNF3
The PS2<2:0> bits set the length, in TQ’s, of PS2, if the
CNF2.BTLMODE bit is set to a ‘1’. If the BTLMODE bit
is set to a ‘0’, the PS2<2:0> bits have no effect.
Additionally, the wake-up filter (CNF3.WAKFIL) is
implemented in the CNF3 register. This filter is a low-
pass filter that can be used to prevent the MCP2502X/
5X from waking up due to short glitches on the CAN
bus.
REGISTER 2-3:
CNF1 - CAN CONFIGURATION REGISTER 1
R/W-0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
bit 7
bit 0
bit 7-6
SJW1:SJW0: Synchronized Jump Width bits
11
= Length = 4 x TQ
10
= Length = 3 x TQ
01
= Length = 2 x TQ
00
= Length = 1 x TQ
bit 5-0
BRP5:BRP0: Baud Rate Prescaler bits
111111
=TQ = 2 x 64 x 1/FOSC
-
000000
=TQ = 2 x 1 x 1/FOSC
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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