The base TQ is defined as t" />
參數(shù)資料
型號(hào)： MCP25020-E/P
廠商： Microchip Technology
文件頁(yè)數(shù)： 65/66頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER CAN 8B 14DIP
標(biāo)準(zhǔn)包裝： 30
接口： CAN
輸入/輸出數(shù)： 8
中斷輸出： 無(wú)
頻率 - 時(shí)鐘： 25MHz
電源電壓： 4.5 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 通孔
封裝/外殼： 14-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 14-PDIP
包裝： 管件
包括： 存儲(chǔ)器，PWM
配用： MCP2515DM-PCTL-ND - BOARD DEMO FOR MCP2515
DV250501-ND - KIT DEV CAN MCP250XX
其它名稱(chēng)： MCP25020E/P
MCP2502X/5X
DS21664D-page 8
2007 Microchip Technology Inc.
The base TQ is defined as twice the oscillator period.
Adding the BRP into the equation yields:
By definition, the nominal bit time is programmable
from a minimum of 8 TQ to 25 TQ. Also, the minimum
nominal bit time is 1 s, which corresponds to 1 Mb/s.
2.4.2
TIME SEGMENTS
Time segments make up the nominal bit time. The
nominal bit time can be thought of as being divided into
separate non-overlapping time
segments.
These
segments are shown in Figure 2-3.
Synchronization Segment (SyncSeg)
Propagation Segment (PropSeg)
Phase Buffer Segment 1 (PS1)
Phase Buffer Segment 2 (PS2)
Rules for Programming the Segments
There are a few rules to follow when programming the
time segments:
PropSeg + PS1
≥ PS2
PS2 > Sync Jump Width
PS2
≥ Information Processing Time
2.4.2.1
Synchronization Segment
This part of the bit time is used to synchronize the
various CAN nodes on the bus. The edge of the input
signal is expected to occur during the SyncSeg. The
duration is fixed at 1 TQ.
2.4.2.2
Propagation Segment
This part of the bit time is used to compensate for
physical delay times within the network. These delay
times consist of the signal propagation time on the bus
line and the internal delay time of the nodes. The delay
is calculated as being the round-trip time from
transmitter to receiver (twice the signal's propagation
time on the bus line), the input comparator delay and
the output driver delay. The length of the Propagation
Segment can be programmed from 1 TQ to 8 TQ by
setting the PRSEG2:PRSEG0 bits of the CNF2
register.
2.4.2.3
Phase Buffer Segments
The Phase Buffer Segments are used to optimally
locate the sampling point of the received bit within the
nominal bit time. The sampling point occurs between
PS1 and PS2. These segments can be automatically
lengthened or shortened by the resynchronization
process. Thus, the variation of the values of the phase
buffer segments represent the DPLL functionality.
Phase Segment 1 (PS1): The end of PS1 determines
the sampling point within a bit time. PS1 is programma-
ble from 1 TQ - 8 TQ in duration.
Phase Segment 2 (PS2): PS2 provides delay before
the next transmitted data transition and is also pro-
grammable from 1 TQ - 8 TQ in duration. However, due
to IPT requirements, the actual minimum length of
phase segment 2 is 2 TQ. It may also be defined to be
equal to the greater of PS1 or the information process-
ing time (IPT).
2.4.3
SAMPLE POINT
The sample point is the point of time at which the bus
level is read and the value of the received bit is
determined. The sampling point occurs at the end of
PS1. If desired, it is possible to specify multiple
sampling of the bus line at the sample point. The value
of the received bit is determined to be the value of the
majority decision of three values. The three samples
are taken at the sample point, and twice before, with a
time of TQ/2 between each sample.
2.4.4
INFORMATION PROCESSING TIME
The Information Processing Time (IPT) is the time
segment (starting at the sample point) that is reserved
for calculation of the subsequent bit level. The CAN
specification defines this time to be less than or equal
to 2 TQ. The MCP2502X/5X defines this time to be
2TQ. Thus, PS2 must be at least 2 TQ long.
2.4.5
SYNCHRONIZATION JUMP WIDTH
To
compensate
for
phase
shifts
and
oscillator
tolerances between the nodes in the system, each
CAN controller must be able to synchronize to the
relevant signal edge of the incoming signal. When a
recessive-to-dominant edge in the transmitted data is
detected, the logic will compare the location of the edge
to the expected time (SyncSeg). The circuit will then
adjust the values of PS1 and PS2, as necessary, using
the programmed Synchronization Jump Width (SJW).
This adjustment is made for resynchronization during a
message and not hard synchronization, which occurs
only at the message Start-of-Frame (SOF).
T
Q
2*T
OSC * BRP
1
+
()
=
where BRP = binary value represented by
CNF1.BRP<5:0>
Nominal Bit Time
T
Q* Sync_Seg
PropSeg
Phase_Seg1
Phase_Seg2
+
++
(
)
=
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