MCP2021A/2A
DS22298A-page 18
2012 Microchip Technology Inc.
Bus Interface (DC specifications are for a VBB range of 6.0 to 18.0V)
High Level Input Voltage
VIH(LBUS)
0.6 VBB
—
V
Recessive state
Low Level Input Voltage
VIL(LBUS)-8
—
0.4 VBB
V
Dominant state
Input Hysteresis
VHYS
—
0.175 VBB
VVIH(LBUS) – VIL(LBUS)
Low Level Output Current
IOL(LBUS)
40
—
200
mA
Output voltage = 0.1 VBB,
VBB = 12V
Pull-up Current on Input
IPU(LBUS)-180
—
-72
A
~30 k
internal pull-up
@ VIH (LBUS) = 0.7 VBB,
VBB=12V
Short Circuit Current Limit
ISC
50
—
200
mA
High Level Output Voltage
VOH(LBUS)
0.8 VBB
—VBB
V
Driver Dominant Voltage
V_LOSUP
——
1.1
V
VBB = 7.3V, RLOAD =
1000
Driver Dominant Voltage
V_HISUP
——
1.2
V
VBB = 18V,
RLOAD = 1000
Input Leakage Current
(at the receiver during
dominant bus level)
IBUS_PAS_DOM
-1
—
mA
Driver off,
VBUS = 0V,
VBB = 12V
Input Leakage Current
(at the receiver during
recessive bus level)
IBUS_PAS_REC
-20
—
20
A
Driver off,
8V < VBB < 18V
8V < VBUs < 18V
VBUS
VBB
Leakage Current
(disconnected from ground)
IBUS_NO_GND
-10
—
+10
A
GNDDEVICE = VBB,
0V < VBUS < 18V,
VBB = 12V
Leakage Current
(disconnected from VBB)
IBUS_NO_PWR
-10
—
+10
A
VBB = GND,
0 < VBUS < 18V
Receiver Center Voltage
VBUS_CNT
0.475 VBB
0.5
VBB
0.525 VBB
VVBUS_CNT = (VIL (LBUS) +
VIH (LBUS))/2
Slave Termination
RSLAVE
20
30
47
k
Capacitance of slave node
CSLAVE
50
pF
Wake-Up Voltage Thresh-
old on LIN Bus
VWK(LBUS)
—
3.4
V
Wake up from POWER-
Note 1:
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0
, TX = 0, VLBUS = VBB).
2:
For design guidance only, not tested.
3:
In POWER DOWN mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to
detect bus activities.
2.3
DC Specifications (Continued)
DC Specifications
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
TA = -40°C to +125°C
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions