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參數(shù)資料
| 型號： | MCM8A10 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1M x 8 Bit Fast Static RAM Module |
| 中文描述： | 100萬× 8位快速靜態(tài)存儲器模塊 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 79K |
| 代理商： | MCM8A10 |
MCM8A10
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 ns
1.5 V
. . . . . . . . . . . . . . .
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . .
See Figure 1a
READ CYCLE TIMING
(See Notes 1 and 2)
Parameter
Symbol
b l
MCM8A10–15
U i
Unit
Notes
Min
Max
Read Cycle Time
tAVAV
tAVQV
tELQV
tAXQX
tELQX
tEHQZ
15
—
ns
2, 3
Address Access Time
—
15
ns
Enable Access Time
—
15
ns
4
Output Hold from Address Change
5
—
ns
Enable Low to Output Active
5
—
ns
5, 6, 7
Enable High to Output High–Z
0
6
ns
5, 6, 7
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low.
5. At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E
≤
VIL).
(a)
(b)
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de-
vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
TIMING LIMITS
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
5 pF
+ 5 V
OUTPUT
255
480
Figure 1. AC Test Loads
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