參數(shù)資料
型號： MCM69L736AZP8.5
廠商： MOTOROLA INC
元件分類： SRAM
英文描述： Circular Connector; Body Material:Aluminum; Series:PT07; Number of Contacts:3; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Jam Nut Receptacle; Circular Contact Gender:Pin; Insert Arrangement:12-3
中文描述： 128K X 36 CACHE SRAM, 8.5 ns, PBGA119
封裝： 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
文件頁數(shù)： 8/20頁
文件大小： 225K
代理商： MCM69L736AZP8.5
MCM69L736A
MCM69L818A
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(0 C
≤
TA
≤
70 C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
0.25 to 1.25 V
1 V/ns (20% to 80%)
. . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
0.75 V
Output Timing Reference Level
Clock Input Timing Reference Level
RQ for 50
Impedance
0.75 V
. . . . . . . . . . . . . . . . . . . . . . . . .
Differential Cross–Point
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
250
READ/WRITE CYCLE TIMING
(See Note 3)
MCM69L736A–7.5
MCM69L818A–7.5
MCM69L736A–8.5
MCM69L818A–8.5
MCM69L736A–9.5
MCM69L818A–9.5
MCM69L736A–10.5
MCM69L818A–10.5
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQV
7
—
8
—
9
—
10
—
ns
Clock High Pulse Width
2.8
—
3.2
—
3.6
—
4
—
ns
Clock Low Pulse Width
2.8
—
3.2
—
3.6
—
4
—
ns
Clock High to Output
Valid
—
7.5
—
8.5
—
9.5
—
10.5
ns
2
Clock Low to Output
Valid
tKLQV
—
3.5
—
4
—
4
—
4
ns
2
Clock Low to Output
Hold
tKLQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
2
Clock Low to Output
Low–Z
tKLQX1
1
—
1
—
1
—
1
—
ns
3
Clock High to Output
High–Z
tKHQZ
—
3.5
—
4
—
4
—
4
ns
3
Output Enable Low to
Output Low–Z
tGLQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
3
Output Enable Low to
Output Valid
tGLQV
—
3.5
—
4
—
4
—
4
ns
2
Output Enable to Output
Hold
tGHQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
2
Output Enable High to
Output High–Z
tGHQZ
—
3.5
—
4
—
4
—
4
ns
3
Setup Times:
Address
Data In
Chip Select
Write Enable
tAVKH
tDVKH
tSVKH
tWVKH
tKHAX
tKHDX
tKHSX
tKHWX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Hold Times:
Address
Data In
Chip Select
Write Enable
1
—
1
—
1
—
1
—
ns
NOTES:
1. Measured at
±
200 mV from steady state.
2. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications
(e.g., tKHKL) or at frequencies that exceed the applied K clock frequency.
3. Tested per AC Test Load diagram. See Figure 1.
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, ad-
dress setup time is shown as a minimum since the system
must supply at least that much time. On the other hand, re-
sponses from the memory are specified from the device
point of view. Thus, the access time is shown as a maximum
since the device never provides data later than that time.
TIMING LIMITS
DEVICE
UNDER
TEST
ZQ
50
50
0.75 V
VDDQ/2
Vref
250
Figure 1. AC Test Load
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