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參數(shù)資料
| 型號： | MCM6949YJ8R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 4 Bit Static Random Access Memory |
| 中文描述： | 1M X 4 STANDARD SRAM, 8 ns, PDSO32 |
| 封裝： | 0.400 INCH, SOJ-32 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 122K |
| 代理商： | MCM6949YJ8R |
MCM6949
1
MOTOROLA FAST SRAM
Motorola, Inc. 1998
Advance Information
1M x 4 Bit Static Random
Access Memory
The MCM6949 is a 4,194,304 bit static random access memory organized as
1,048,576 words of 4 bits. Static design eliminates the need for external clocks
or timing strobes.
The MCM6949 is equipped with chip enable (E) and output enable (G) pins,
allowing for greater system flexibility and eliminating bus contention problems.
Either input, when high, will force the outputs into high–impedance.
The MCM6949 is available in a 400 mil, 32–lead surface–mount SOJ package.
Single 3.3 V – 5%, + 10% Power Supply
Fast Access Time: 8/10/12/15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Three–State Outputs
Power Operation: 195/165/160/155 mA Maximum, Active AC
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MCM6949/D
SEMICONDUCTOR TECHNICAL DATA
MCM6949
A0 – A19
W
. . . . . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . . . . .
E
. . . . . . . . . . . . . . . . . . . . . . . . .
DQ
. . . . . . . . . . . . . . . . . .
NC
. . . . . . . . . . . . . . . . . . . . .
VCC
. . . . . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . . . . .
Address Inputs
Write Enable
Output Enable
Chip Enable
Data Input/Output
No Connection
+ 3.3 V Power Supply
. . . . . . . . . . . . . . . .
Ground
PIN NAMES
YJ PACKAGE
400 MIL SOJ
CASE 857A–02
REV 4
4/2/98
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