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參數(shù)資料
| 型號： | MCM62486BFN19 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | Replaced by PTH12000W : |
| 中文描述： | 32K X 9 CACHE SRAM, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 197K |
| 代理商： | MCM62486BFN19 |
MCM62486B
3
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE
(See Notes 1, 2, 3, and 4)
S
ADSP
ADSC
ADV
W
K
Address Used
Operation
F
L
X
X
X
L–H
N/A
Deselected
F
X
L
X
X
L–H
N/A
Deselected
T
L
X
X
X
L–H
External Address
Read Cycle, Begin Burst
T
H
L
X
L
L–H
External Address
Write Cycle, Begin Burst
T
H
L
X
H
L–H
External Address
Read Cycle, Begin Burst
X
H
H
L
L
L–H
Next Address
Write Cycle, Continue Burst
X
H
H
L
H
L–H
Next Address
Read Cycle, Continue Burst
X
H
H
H
L
L–H
Current Address
Write Cycle, Suspend Burst
X
H
H
H
H
L–H
Current Address
Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except G must meet setup and hold times for the low–to–high transition of clock (K).
3. S represents S0 and S1. T implies S1 = L and S0 = H; F implies S1 = H or S0 = L.
4. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2)
Operation
G
I/O Status
Read
L
Data Out (DQ0 – DQ8)
Read
H
High–Z
Write
X
High–Z — Data In (DQ0 – DQ8)
Deselected
X
High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G must be high before the input data
required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS = 0)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
VCCQ
Vin, Vout
Iout
PD
Tbias
TA
Tstg
– 0.5 to 7.0
V
Output Power Supply Voltage
– 0.5 to VCC
– 0.5 to VCC + 0.5
±
20
V
Voltage Relative to VSS
Output Current (per I/O)
V
mA
Power Dissipation
1.0
W
Temperature Under Bias
– 10 to + 85
°
C
Operating Temperature
0 to + 70
°
C
Storage Temperature
– 55 to + 125
°
C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad-
vised that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This CMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
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