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參數(shù)資料
| 型號： | MCM6226BB |
| 廠商： | Motorola, Inc. |
| 英文描述： | 128K x 8 Bit Static Random Access Memory |
| 中文描述： | 128K的× 8位靜態(tài)隨機存取存儲器 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 156K |
| 代理商： | MCM6226BB |
MCM6226BB
1
Motorola, Inc. 1996
128K x 8 Bit Static Random
Access Memory
The MCM6226BB is a 1,048,576 bit static random access memory organized
as 131,072 words of 8 bits. Static design eliminates the need for external clocks
or timing strobes while CMOS circuitry reduces power consumption and provides
for greater reliability.
The MCM6226BB is equipped with both chip enable (E1 and E2) and output
enable (G) pins, allowing for greater system flexibility and eliminating bus conten-
tion problems.
The MCM6226BB is available in 300 mil and 400 mil, 32 lead surface–mount
SOJ packages.
Single 5 V
±
10% Power Supply
Fast Access Times: 15/17/20/25/35 ns
Equal Address and Chip Enable Access Times
All Inputs and Outputs are TTL Compatible
Three State Outputs
Low Power Operation: 190/180/165/150/130 mA Maximum, Active AC
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
MEMORY MATRIX
512 ROWS x
2048 COLUMNS
ROW
DECODER
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
DQ
DQ
A
A
E1
E2
W
G
Order this document
by MCM6226BB/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6226BB
EJ PACKAGE
300 MIL SOJ
CASE 857–02
A
W
G
E1, E2
DQ
NC
VCC
VSS
Address Inputs
Write Enable
Output Enable
Chip Enables
Data Inputs/Outputs
No Connection
+ 5 V Power Supply
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Ground
PIN NAMES
DQ
VSS
NC
A
A
A
A
A
A
A
A
A
A
A
DQ
DQ
VCC
A
E2
W
A
A
A
G
A
E1
DQ
DQ
DQ
A
DQ
23
22
21
20
19
32
31
30
29
28
27
26
25
24
18
17
15
16
10
11
12
13
14
1
2
3
4
5
6
7
8
9
XJ PACKAGE
400 MIL SOJ
CASE 857A–02
DQ
REV 2
10/31/96
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