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參數(shù)資料
| 型號(hào)： | MCIMX515DVK8C |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 180/202頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU I.MX51 527MABGA |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | i.MX51 |
| 核心處理器： | ARM? Cortex?-A8 |
| 芯體尺寸： | 32-位 |
| 速度： | 800MHz |
| 連通性： | 1 線，EBI/EMI，以太網(wǎng)，I²C，IrDA，MMC，SPI，SSI，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 128 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 128K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 0.8 V ~ 1.15 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -20°C ~ 85°C |
| 封裝/外殼： | 527-LFBGA |
| 包裝： | 托盤 |
Electrical Characteristics
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
79
4.7.4
FEC AC Timing Parameters
This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC
is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver
interface and transceiver function are required to complete the interface to the media. The FEC supports
the 10/100 Mbps MII (18 pins in total) and the 10 Mbps-only 7-wire interface, which uses 7 of the MII
pins, for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, see i.MX51
Multimedia Applications Processor Reference Manual (MCIMX51RM).
This section describes the AC timing specifications of the FEC.
4.7.4.1
MII Receive Signal Timing
The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must
exceed twice the FEC_RX_CLK frequency. Table 70 lists the MII receive channel signal timing
parameters and Figure 43 shows MII receive signal timings.
.
SD7
eSDHC Input Setup Time
tISU
2.5
—
ns
SD8
eSDHC Input Hold Time
tIH
5
2.5
—
ns
1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2 In normal speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode, clock
frequency can be any value between 0
–50 MHz.
3 In normal speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0
–52 MHz.
4 Measurement taken with CLoad = 20 pF
5 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
Table 70. MII Receive Signal Timing
Num
Characteristic1
1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.
Min
Max
Unit
M1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
—
ns
M2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
—
ns
M3
FEC_RX_CLK pulse width high
35%
65%
FEC_RX_CLK period
M4
FEC_RX_CLK pulse width low
35%
65%
FEC_RX_CLK period
Table 69. eSDHCv2 Interface Timing Specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
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