參數(shù)資料
型號: MCIMX357DJQ5C
廠商: Freescale Semiconductor
文件頁數(shù): 58/147頁
文件大小: 0K
描述: MULTIMEDIA PROCESSOR 400-MAPBGA
標準包裝: 90
系列: i.MX35
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB OTG
外圍設備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振蕩器型: 外部
工作溫度: -20°C ~ 70°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
18
System Reset (using the RESET_IN_B pin)
4.4.1
Power On Reset
POR_B is normally connected to a power management integrated circuit (PMIC). The PMIC asserts
POR_B while the power supplies are turned on and negates POR_B after the power up sequence is
finished. See Figure 2.
Assuming the i.MX35 chip is already fully powered; it is still possible to reset all of the modules to their
default reset by asserting POR_B for at least 4 CKIL cycles and later de-asserting POR_B. This method
of resetting the i.MX35 can also be supported by tying the POR_B and RESET_IN_B pins together.
Figure 3. Timing Between POR_B and CKIL for Complete Reset of i.MX35
4.4.2
System Reset
System reset can be achieved by asserting RESET_IN_B for at least 4 CKIL cycles and later negating
RESET_IN_B. The following modules are not reset upon system reset: RTC, PLLs, CCM, and IIM.
POR_B pin must be deasserted all the time.
Figure 4. Timing Between RESET_IN_B and CKIL for i.MX35 System Reboot
4.5
Power Characteristics
The table shows values representing maximum current numbers for the i.MX35 under worst case voltage
and temperature conditions. These values are derived from the i.MX35 with core clock speeds up to
POR_B
CKIL
At least 4 CKIL cycles
RESET_IN_B
CKIL
At least 4 CKIL cycles
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