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寤犲晢锛� Freescale Semiconductor
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i.MX35 Applications Processors for Automotive Products, Rev. 10
Freescale Semiconductor
82
DI_DISPn_TIME_CONF_3 registers (n = 0,1,2). Figure 57 shows the timing of the parallel interface with
read wait states.
Figure 57. Parallel Interface Timing Diagram鈥擱ead Wait States
4.9.13.4.9
Parallel Interfaces, Electrical Characteristics
Figure 58, Figure 60, Figure 59, and Figure 61 depict timing of asynchronous parallel interfaces based on
the system 80 and system 68k interfaces. Table 58 lists the timing parameters at display access level. All
WRITE OPERATION
READ OPERATION
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISP0_RD_WAIT_ST=00
DISP0_RD_WAIT_ST=01
DISP0_RD_WAIT_ST=10
鐩搁棞PDF璩囨枡
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