參數(shù)資料
型號: MCIMX353CJQ5CR2
廠商: Freescale Semiconductor
文件頁數(shù): 100/147頁
文件大小: 0K
描述: MULTIMEDIA PROCESSOR 400-MAPBGA
標準包裝: 90
系列: i.MX35
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 帶卷 (TR)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
56
4.9.6
Enhanced Serial Audio Interface (ESAI) Timing Specifications
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator. Table 46 shows the interface timing values. The number field in the table refers to timing signals
Table 46. Enhanced Serial Audio Interface Timing
No.
Characteristics1,2
Symbol
Expression2
Min.
Max.
Condition3 Unit
62
Clock cycle4
tSSICC
4
× T
c
4
× T
c
30.0
i ck
ns
63
Clock high period
For internal clock
—2
× Tc 9.0
6
ns
For external clock
2
× T
c
15
64
Clock low period
For internal clock
—2
× T
c 9.0
6
ns
For external clock
2
× Tc
15
65
SCKR rising edge to FSR out (bl) high
17.0
7.0
x ck
i ck a
ns
66
SCKR rising edge to FSR out (bl) low
17.0
7.0
x ck
i ck a
ns
67
SCKR rising edge to FSR out (wr) high5
19.0
9.0
x ck
i ck a
ns
68
SCKR rising edge to FSR out (wr) low5
19.0
9.0
x ck
i ck a
ns
69
SCKR rising edge to FSR out (wl) high
16.0
6.0
x ck
i ck a
ns
70
SCKR rising edge to FSR out (wl) low
17.0
7.0
x ck
i ck a
ns
71
Data in setup time before SCKR (SCK in synchronous
mode) falling edge
12.0
19.0
x ck
i ck
ns
72
Data in hold time after SCKR falling edge
3.5
9.0
x ck
i ck
ns
73
FSR input (bl, wr) high before SCKR falling edge5
2.0
12.0
x ck
i ck a
ns
74
FSR input (wl) high before SCKR falling edge
2.0
12.0
x ck
i ck a
ns
75
FSR input hold time after SCKR falling edge
2.5
8.5
x ck
i ck a
ns
78
SCKT rising edge to FST out (bl) high
18.0
8.0
x ck
i ck
ns
79
SCKT rising edge to FST out (bl) low
20.0
10.0
x ck
i ck
ns
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