參數(shù)資料
型號： MCIMX31LDVMN5D
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 532 MHz, MICROPROCESSOR, PBGA473
封裝： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-473
文件頁數(shù)： 107/118頁
文件大?。?/td> 1083K
代理商： MCIMX31LDVMN5D
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
89
The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides
a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the
TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins.
There is no timing relationship between the clock and the data. The clock that the SIM module provides
to the aim card will be used by the SIM card to recover the clock from the data much like a standard UART.
All six (or 5 in case bi-directional TXRX is used) of the pins for each half of the SIM module are
asynchronous to each other.
There are no required timing relationships between the signals in normal mode, but there are some in two
specific cases: reset and power down sequences.
4.3.20.1
General Timing Requirements
Figure 72 shows the timing of the SIM module, and Figure 56 lists the timing parameters.
Figure 72. SIM Clock Timing Diagram
4.3.20.2
Reset Sequence
4.3.20.2.1
Cards with Internal Reset
The sequence of reset for this kind of SIM Cards is as follows (see Figure 73):
After powerup, the clock signal is enabled on SGCLK (time T0)
After 200 clock cycles, RX must be high.
The card must send a response on RX acknowledging the reset between 400 and 40000 clock
cycles after T0.
Table 56. SIM Timing Specification—High Drive Strength
Num
Description
Symbol
Min
Max
Unit
1
SIM Clock Frequency (CLK)1
1 50% duty cycle clock
Sfreq
0.01
5 (Some new cards
may reach 10)
MHz
2
SIM CLK Rise Time 2
2 With C = 50pF
Srise
—20
ns
3
SIM CLK Fall Time 3
3 With C = 50pF
Sfall
—20
ns
4
SIM Input Transition Time (RX, SIMPD)
Strans
—25
ns
CLK
Srise
Sfall
1/Sfreq
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