參數(shù)資料
型號(hào): MCIMX31DVMN5D
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 532 MHz, MICROPROCESSOR, PBGA473
封裝: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-473
文件頁(yè)數(shù): 106/118頁(yè)
文件大?。?/td> 1083K
代理商: MCIMX31DVMN5D
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MCIMX31/MCIMX31L Technical Data, Rev. 4.3
88
Freescale Semiconductor
Electrical Characteristics
Figure 71. SDHC Timing Diagram
4.3.20
SIM Electrical Specifications
Each SIM card interface consist of a total of 12 pins (for 2 separate ports of 6 pins each. Mostly one port
with 5 pins is used).
Table 55. SDHC Interface Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
Card Input Clock
SD1
Clock Frequency (Low Speed)
fPP
1
1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 V–3.3 V.
0
400
kHz
Clock Frequency (SD/SDIO Full Speed)
fPP
2
2 In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 MHz–25 MHz.
025
MHz
Clock Frequency (MMC Full Speed)
fPP
3
3 In normal data transfer mode for MMC card, clock frequency can be any value between 0 MHz–20 MHz.
020
MHz
Clock Frequency (Identification Mode)
fOD
4
4 In card identification mode, card clock must be 100 kHz–400 kHz, voltage ranges from 2.7 V–3.3 V.
100
400
kHz
SD2
Clock Low Time
tWL
10
ns
SD3
Clock High Time
tWH
10
ns
SD4
Clock Rise Time
tTLH
—10
ns
SD5
Clock Fall Time
tTHL
—10
ns
SDHC Output/Card Inputs CMD, DAT (Reference to CLK)
SD6
SDHC output delay
tODL
–6.5
3
ns
SDHC Input/Card Outputs CMD, DAT (Reference to CLK)
SD7
SDHC input setup
tIS
—18.5
ns
SD8
SDHC input hold
tIH
–11.5
ns
SD1
SD5
SD7
SD4
SD8
CMD
Output from SDHC to card
DATA[3:0]
Input to SDHC
CLK
SD2
SD6
SD3
CMD
DATA[3:0]
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