參數(shù)資料
型號: MCIMX31DVKN5D
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 532 MHz, MICROPROCESSOR, PBGA457
封裝: 14 X 14 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-457
文件頁數(shù): 68/118頁
文件大小: 1083K
代理商: MCIMX31DVKN5D
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
53
Figure 40 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and
Table 40 lists the timing parameters.
Figure 40. Trace Data Timing Diagram
4.3.10.1
Half-Rate Clocking Mode
When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and
falling edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 40.
4.3.11
FIR Electrical Specifications
FIR implements asynchronous infrared protocols (FIR, MIR) that are defined by IrDA
(Infrared Data
Association). Refer to http://www.IrDA.org for details on FIR and MIR protocols.
4.3.12
Fusebox Electrical Specifications
Table 39. ETM TRACECLK Timing Parameters
ID
Parameter
Min
Max
Unit
Tcyc
Clock period
Frequency dependent
ns
Twl
Low pulse width
2
ns
Twh
High pulse width
2
ns
Tr
Clock and data rise time
3
ns
Tf
Clock and data fall time
3
ns
Table 40. ETM Trace Data Timing Parameters
ID
Parameter
Min
Max
Unit
Ts
Data setup
2
ns
Th
Data hold
1
ns
Table 41. Fusebox Timing Characteristics
Ref. Num
Description
Symbol
Minimum
Typical
Maximum
Units
1
Program time for eFuse1
1 The program length is defined by the value defined in the epm_pgm_length[2:0] bits of the IIM module. The value to program
is based on a 32 kHz clock source (4 * 1/32 kHz = 125 s).
tprogram
125
s
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