參數(shù)資料
型號： MCIMX27MOP4A
廠商： Freescale Semiconductor
文件頁數(shù)： 68/152頁
文件大小： 0K
描述： IC MPU I.MX27 19X19 473MAPBGA
標(biāo)準(zhǔn)包裝： 84
系列： i.MX27
核心處理器： ARM9
芯體尺寸： 32-位
速度： 400MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，LCD，POR，PWM，WDT
程序存儲器類型： ROMless
RAM 容量： 45K x 8
電壓 - 電源 (Vcc/Vdd)： 1.38 V ~ 1.52 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 473-LFBGA
包裝： 托盤
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
22
Freescale Semiconductor
Functional Description and Application Information
factor, pin assignment, and data transfer protocol are forward-compatible with the MultiMedia Card with
some additions. Under SD, it can be categorized into Memory and I/O. The memory card invokes a
copyright protection mechanism that complies with the security of the SDMI standard, which is faster and
provides the capability for a higher memory capacity. The I/O card provides high-speed data I/O with
low-power consumption for mobile electronic devices.
2.3.33
Smart Liquid Crystal Display Controller Module (SLCDC)
The Smart Liquid Crystal Display Controller (SLCDC) module transfers data from the display memory
buffer to the external display device. Direct Memory Access (DMA) transfers the data transparently with
minimal software intervention. Bus utilization of the DMA is controllable and deterministic.
As cellular phone displays become larger and more colorful, demands on the processor increase. More
CPU power is needed to render and manage the image. The role of the display controller is to reduce the
CPU’s involvement in the transfer of data from memory to the display device so the CPU can concentrate
on image rendering. DMA is used to optimize the transfer. Embedded control information needed by the
display device is automatically read from a second buffer in system memory and inserted into the data
stream at the proper time to completely eliminate the CPU’s role in the transfer.
A typical scenario for a cellular phone display is to have the display image rendered in main system
memory. After the image is complete, the CPU triggers the SLCDC module to transfer the image to the
display device. Image transfer is accomplished by burst DMA, which steals bus cycles from the CPU.
Cycle-stealing behavior is programmable so bus use is kept within predefined bounds. After the transfer
is complete, a maskable interrupt is generated indicating the status. For animated displays, it is suggested
that a two-buffer ping-pong scheme be implemented so that the DMA is fetching data from one buffer
while the next image is rendered into the other.
Several display sizes and types are used in the various products that use the SLCDC. The SLCDC module
has the capability of directly interfacing to the selected display devices. Both serial and parallel interfaces
are supported. The SLCDC module only supports writes to the display controller. SLCDC read operations
from the display controller are not supported.
2.3.34
Synchronous Serial Interface (SSI)
The Synchronous Serial Interface (SSI) is a full-duplex serial port that allows the chip to communicate
with a variety of serial devices. These serial devices can be standard codecs, Digital Signal Processors
(DSPs), microprocessors, peripherals, and popular industry audio codecs that implement the inter-IC
sound bus standard (I2S) and Intel AC97 standard.
The SSI is typically used to transfer samples in a periodic manner. The SSI consists of independent
transmitter and receiver sections with independent clock generation and frame synchronization.
The SSI contains independent (asynchronous) or shared (synchronous) transmit and receive sections with
separate or shared internal/external clocks and frame syncs, operating in Master or Slave mode. The SSI
can work in Normal mode operation using frame sync, and in Network mode operation allowing multiple
devices to share the port with as many as thirty-two time slots.
The SSI provides two sets of Transmit and Receive FIFOs. Each of the four FIFOs is 8
× 24 bits. The two
sets of Tx/RX FIFOs can be used in Network mode to provide two independent channels for transmission
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