參數(shù)資料
型號(hào): MCIMX257DVM4
廠商: Freescale Semiconductor
文件頁數(shù): 63/153頁
文件大小: 0K
描述: IC MPU I.MX25 COMM 400MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: i.MX25
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 128
程序存儲(chǔ)器類型: 外部程序存儲(chǔ)器
RAM 容量: 144K x 8
電壓 - 電源 (Vcc/Vdd): 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x12b
振蕩器型: 外部
工作溫度: -20°C ~ 70°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
17
NOTE
The user is advised to connect FUSEVDD to GND except when fuses
are programmed, to prevent unintentional blowing of fuses.
Other power-up sequences may be possible; however, the above
sequence has been verified and is recommended.
There is a 1 ms minimum time between supplies coming up, and a 1 ms
minimum time between POR_B assert and de-assert.
The dV/dT should be no faster than 0.25 V/
μs for all power supplies, to
avoid triggering ESD circuit.
Figure 2 shows the power-up sequence diagram. After POR_B is asserted, Core VDD and NVDDx can be
powered up. After Core VDD and NVDDx are stable, the analog supplies can be powered up.
Figure 2. Power-Up Sequence Diagram
3.2.2
Power-Down Sequence
There are no special requirements for the power-down sequence. All power supplies can be shut down at
the same time.
3.2.3
SRTC DryIce Power-Up/Down Sequence
In order to guarantee DryIce power-loss protection, including retention of SRTC time data during power
down, users must do the following:
Place a proper capacitor on the NVCC_DRYICE output pin, and
Implement the below power-up/down sequence
1. Assert power on reset (POR).
2. Turn on NVCC_CRM.
3. Turn on QVDD digital logic domain supplies for not less than 1 ms and not more than 32 ms, after
NVCC_CRM reaches 90% of 3.3 V.
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