參數(shù)資料
型號(hào): MCIMX251AJM4
廠商: Freescale Semiconductor
文件頁數(shù): 76/140頁
文件大?。?/td> 0K
描述: IC MPU IMX25 AUTO 400MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: i.MX25
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 128
程序存儲(chǔ)器類型: 外部程序存儲(chǔ)器
RAM 容量: 144K x 8
電壓 - 電源 (Vcc/Vdd): 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX25 Applications Processor for Automotive Products, Rev. 10
40
Freescale Semiconductor
Table 31 shows the AC requirements for DDR2 I/O.
Output pad propagation delay1, 40%–60% input
signals and crossing of output signals
tpo
25 pF
50 pF
1.47/1.38
1.75/1.67
2.13/2.00
2.54/2.40
3.072/2.87
3.65/3.45
ns
Output enable to output valid delay, 50%–50%1
tpv
25 pF
50 pF
1.32/1.28
1.66/1.65
2.11/2.00
2.61/2.50
3.31/3.12
4.06/3.81
ns
Output enable to output valid delay, 40%–60%1
tpv
25 pF
50 pF
1.40/1.37
1.67/1.66
2.16/2.06
2.56/2.45
3.30/3.13
3.89/3.67
ns
Output pad slew rate2
tps
25 pF
50 pF
0.86/0.98
0.46/054
1.35/1.5
0.72/0.81
2.15/2.19
1.12/1.16
V/ns
Output pad dI/dt3
tdit
25 pF
50 pF
72
77
172
183
400
422
mA/ns
Input pad transition times4
trfi
1.0 pF
0.07/0.08
0.10/0.12
0.17/0.20
ns
Input pad propagation delay, 50%–50%4
tpi
1.0 pF
0.89/0.87
1.41/1.37
2.16/2.07
ns
Input pad propagation delay, 40%–60%4
tpi
1.0 pF
1.71/1.69
2.22/2.18
2.98/2.88
ns
1 Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs
model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
2 Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
3 Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.
4 Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.7 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
Table 31. AC Requirements for DDR2 I/O
Parameter1
1 The Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any specification in
this document.
Symbol
Min.
Max.
Units
AC input logic high
VIH(ac)
OVDD/2 + 0.25
OVDD + 0.3
V
AC input logic low
VIL(ac)
–0.3
OVDD/2 – 0.25
V
AC differential input voltage2
2 Vid(ac) specifies the input differential voltage |Vtr–Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The minimum value is equal to Vih(ac)–Vil(ac)
Vid(ac)
0.5
OVDD + 0.6
V
AC differential cross point voltage for input3
3 The typical value of Vix(ac) is expected to be about 0.5 × OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Vix(ac)
OVDD/2–0.175
OVDD/2 + 0.175
V
AC differential cross point voltage for output4
4 The typical value of Vox(ac) is expected to be about 0.5 × OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)
indicates the voltage at which differential output signal must cross. Cload = 25 pF.
Vox(ac)
OVDD/2–0.125
OVDD/2 + 0.125
V
Table 30. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O (continued)
Parameter
Symbol
Load
Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
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