![](http://datasheet.mmic.net.cn/Freescale-Semiconductor/MC68HC912B32CFU8_datasheet_98749/MC68HC912B32CFU8_55.png)
Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
55
$00FD
Port DLC Control Register
(DLCSCR)(2)
Read:
00
000
BDLCEN
PUPDLC
RDPDLC
Write:
Reset:
00
000
$00FE
Port DLC Data Register
(PORTDLC)(2)
Read:
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
0
UUU
U
$00FF
Port DLC Data Direction Register
(DDRDLC)(2)
Read:
0
DDDLC6
DDDLC5
DDDLC4
DDDLC3
DDDLC2
DDDLC1
DDDLC0
Write:
Reset:
00
000
$0100
msCAN12 Module Control
Register 0 (CMCR0)(3)
Read:
0
CSWAI
SYNCH
TLNKEN
SLPAK
SLPRQ
SFTRES
Write:
Reset:
00
100
001
$0101
msCAN12 Module Control
Register 1 (CMCR1)(3)
Read:
00
000
LOOPB
WUPM
CLKSRC
Write:
Reset:
00
000
$0102
msCAN12 Bus Timing
Register 0 (CBTR0)(3)
Read:
SJW1
SJW0
BRP5
BRP4
BPR3
BPR2
BPR1
BPR0
Write:
Reset:
00
000
$0103
msCAN12 Bus Timing
Register 1 (CBTR1)(3)
Read:
SAMP
TSEG22
TSEG21
TSEG20
TSEG13
TSEG12
TSEG11
TSEG10
Write:
Reset:
00
000
$0104
msCAN12 Receiver Flag
Register (CRFLG)(3)
Read:
WUPIF
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
OVRIF
RXF
Write:
Reset:
00
000
$0105
msCAN12 Receiver Interrupt
Enable Register (CRIER)(3)
Read:
WUPIE
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
OVRIE
RXFIE
Write:
Reset:
00
000
$0106
msCAN12 Transmitter Flag
Register (CTFLG)(3)
Read:
0
ABTAK2
ABTAK1
ABTAK0
0
TXE2
TXE1
TXE0
Write:
Reset:
00
000
111
$0107
msCAN12 Transmitter Control
Register (CTCR)(3)
Read:
0
ABTRQ2
ABTRQ1
ABTRQ0
0
TXEIE2
TXEIE1
TXEIE0
Write:
Reset:
00
000
$0108
msCAN12 Identifier Acceptance
Control Register (CIDAC)(3)
Read:
0
IDAM1
IDAM0
0
IDHIT2
IDHIT1
IDHIT0
Write:
Reset:
00
000
$0109
Reserved
R
↓
Addr.
Register Name
Bit 7
6
543
21
Bit 0
= Unimplemented
R
= Reserved
U = Unaffected
Notes:
1. Available only on MC68HC912B32 and MC68HC912BC32 devices.
2. Available only on MC68HC912B32 and MC68HC12BE32 devices.
3. Available only on MC68HC(9)12BC32 devices.
Figure 2-1. Register Map (Sheet 16 of 19)