參數(shù)資料
型號: MCF5471ZP200
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁數(shù): 3/96頁
文件大?。?/td> 2003K
代理商: MCF5471ZP200
MOTOROLA
MCF547x Integrated Microprocessor Hardware Specifications
11
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MCF547x Family Features
1.4.6.5
I2C (Inter-Integrated Circuit)
The MCF547x product family provides an I2C two-wire, bidirectional serial bus for on-board
communication.
Multimaster operation with arbitration and collision detection
Calling address recognition and interrupt generation
Automatic switching from master to slave on arbitration loss
Software-selectable acknowledge bit
Start and stop signal generation and detection
Bus busy status detection
1.4.6.6
DMA Serial Peripheral Interface (DSPI)
The DSPI block operates as a basic SPI block with FIFOs providing support for external queue operation.
Data to be transmitted and data received reside in separate FIFOs. The FIFOs can be popped and pushed by
host software or by the system DMA controller. The DSPI supports these SPI features:
Full-duplex, three-wire synchronous transfers
Master and slave mode—two peripheral chip selects in master mode
DMA support
1.4.7
DDR SDRAM Memory Controller
The DDR SDRAM memory controller is a glueless interface to DDR memories. The module uses a 32 bit
memory port and can address a maximum of 1 Gbyte of data with sixteen 64M x 8 (512-Mbit) devices, 4
per chip select. The controller supplies two clock lines and respective inverted clock lines to help minimize
system complexity when using DDR. The module supports either DDR or SDR but not both. This is due to
voltage differences between the memory technologies. The supported memory clock rate is up to 133 MHz.
At this memory clock rate, DDR memory can receive data at an effective rate of up to 266 MHz.
Support for up to 13 lines of row address, 11 lines of column address, 2 lines of bank address, and
up to 4 chip selects
Memory bus width fixed at 32 bits
Four chip selects support up to 1 GByte of SDRAM memory
Support for page mode to maximize the data rate. Page mode remembers active pages for all four
chip selects
Support for sleep mode and self refresh
Cache line reads that can use critical word first. These reads can start in the center of a burst and
will wrap to the beginning. This allows the processor quicker access to a needed instruction.
All on-chip bus masters have access to DRAM. This includes PCI, the ColdFire V4e core, the cryptography
accelerator, and the DMA controller.
1.4.8
Peripheral Component Interconnect (PCI)
The PCI controller is a PCI V2.2-compliant bus controller and arbiter. The PCI bus is capable of 66-MHz
operation with a 32-bit address/data bus and support for five external masters.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCF5472 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x Integrated Microprocessor Electrical Characteristics
MCF5472EC 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x ColdFire Microprocessor
MCF5472VR200 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MCF5472ZP200 功能描述:微處理器 - MPU MCF547X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MCF5473 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF547x Integrated Microprocessor Electrical Characteristics