參數(shù)資料
型號: MCF54415CMJ250
廠商: Freescale Semiconductor
文件頁數(shù): 46/61頁
文件大小: 0K
描述: IC MCU 32BIT 256MAPBGA
標(biāo)準(zhǔn)包裝: 450
系列: MCF5441x
核心處理器: Coldfire V4
芯體尺寸: 32-位
速度: 250MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,智能卡,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 87
程序存儲器類型: ROMless
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.14 V ~ 1.32 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor
50
Figure 31. MDIO serial management channel timing diagram
4.23
32-bit timer module timing specifications
Table 35 lists timer module AC timings.
4.24
DSPI timing specifications
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the
transfer attributes are programmable. Table 36 provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the MCF54418 Reference Manual for information on the modified transfer formats used for communicating
with slower peripheral devices.
All DSPI signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load of
50 pF.1
Table 35. Timer module AC timing specifications
Name
Characteristic
Min
Max
Unit
T1
DTnIN cycle time (n =0:3)
3
1/fSYS/2
T2
DTnIN pulse width (n =0:3)
1
1/fSYS/2
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
Table 36. DSPI module AC timing specifications1
Name
Characteristic
Symbol
Min
Max
Unit
Notes
Master Mode
DSPI_SCK frequency
fSCK
—50
MHz
DS1
DSPI_SCK cycle time
tSCK
20
ns
2
DS2
DSPI_SCK duty cycle
(tsck 2) – 2.0
(tsck 2) + 2.0
ns
3
DS3
DSPI_PCSn to DSPI_SCK delay
tCSC
(tsck 2) – 2.0
ns
4
DS4
DSPI_SCK to DSPI_PCSn delay
tASC
(tsck 2) – 3.0
ns
5
DS5
DSPI_SCK to DSPI_SOUT valid
5
ns
MDC (Output)
E11
MDIO (Output)
MDIO (Input)
E11
E12
E13
Valid Data
E14
E15
Valid Data
E10
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