參數(shù)資料
型號: MCF5407
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: ColdFire Integrated Microprocessor(ColdFire微處理器)
中文描述: 32-BIT, 162 MHz, RISC PROCESSOR, PQFP208
封裝: PLASTIC, QFP-208
文件頁數(shù): 8/24頁
文件大?。?/td> 296K
代理商: MCF5407
8
MCF5407 Integrated ColdFire¨ Microprocessor
ColdFire Module Description
The new INTOUCH instruction can be used to prefetch instructions to be locked in the instruction cache
using the cache locking feature. This function may be desirable in certain systems where deterministic real-
time performance is critical.
1.3.2.2 Internal 2-Kbyte SRAMs
The two 2-Kbyte on-chip SRAM modules are also connected to the Harvard memory architecture, and
provide pipelined, single-cycle access to those memory regions mapped to these devices. Each memory can
be independently mapped to any 0-modulo-2K location within the 4-Gbyte address space, and conTgured
to respond either to instruction or to data accesses. Time-critical functions can be mapped onto the
instruction memory bus, while the system stack and/or heavily-referenced data operands can be mapped
onto the data memory bus.
1.3.3 DRAM Controller
The MCF5407 DRAM controller provides a direct interface for up to two blocks of DRAM. The controller
supports 8-, 16-, or 32-bit memory widths, and can easily interface to PC-100 DIMMs. A unique addressing
scheme allows for increases in system memory size without rerouting address lines and rewiring boards.
The controller operates in normal mode or in page mode and supports SDRAMs and EDO DRAMs.
1.3.4 DMA Controller
The MCF5407 provides four fully-programmable DMA channels for quick data transfer. Dual- and single-
address modes provide the ability to program bursting and cycle steal. Data transfers are 32 bits long with
packing and unpacking supported along with an auto-alignment option for efTcient block transfers.
Automatic block transfers from on-chip serial UARTs are also supported through the DMA channels.
1.3.5 UART Modules
The MCF5407 contains two UARTs, which function independently. One UART has been enhanced to
provide synchronous operation and a CODEC interface for soft modem support. Each UART can be clocked
by the system bus clock, eliminating the need for an external crystal. Each UART module interfaces directly
to the CPU, as shown in Figure 2.
Figure 2. UART Module Block Diagram
Serial Communications
Channel
Interrupt Control
Logic
CTS
RTS
RxD
TxD
System bus clock
or
External clock (TIN)
Internal Channel
Control Logic
16-Bit Timer for
Baud-Rate Generation
相關PDF資料
PDF描述
MCM101524 1M x 4 Bit Fast Static Random Access Memory with ECL I/O
MCM101524B12 1M x 4 Bit Fast Static Random Access Memory with ECL I/O
MCM101524B15 1M x 4 Bit Fast Static Random Access Memory with ECL I/O
MCM101525 2M x 2 Bit Fast Static Random Access Memory with ECL I/O
MCM101525B12 2M x 2 Bit Fast Static Random Access Memory with ECL I/O
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