MCF537x ColdFire Microprocessor Data Sheet, Rev. 4 Electrical Characteristics Fr" />
參數(shù)資料
型號(hào): MCF5372LCVM240
廠商: Freescale Semiconductor
文件頁數(shù): 28/46頁
文件大?。?/td> 0K
描述: IC MPU RISC 240MHZ 196-MAPBGA
產(chǎn)品培訓(xùn)模塊: ColdFire® Embedded Voice Solution
標(biāo)準(zhǔn)包裝: 126
系列: MCF537x
核心處理器: Coldfire V3
芯體尺寸: 32-位
速度: 240MHz
連通性: EBI/EMI,以太網(wǎng),I²C,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 62
程序存儲(chǔ)器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 196-LBGA
包裝: 托盤
MCF537x ColdFire Microprocessor Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor
34
Figure 22. QSPI Timing
5.16
JTAG and Boundary Scan Timing
Table 24. JTAG and Boundary Scan Timing
Num
Characteristics1
1 JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
Symbol
Min
Max
Unit
J1
TCLK Frequency of Operation
fJCYC
DC
1/4
fsys/3
J2
TCLK Cycle Period
tJCYC
4—
tCYC
J3
TCLK Clock Pulse Width
tJCW
26
ns
J4
TCLK Rise and Fall Times
tJCRF
03
ns
J5
Boundary Scan Input Data Setup Time to TCLK Rise
tBSDST
4—
ns
J6
Boundary Scan Input Data Hold Time after TCLK Rise
tBSDHT
26
ns
J7
TCLK Low to Boundary Scan Output Data Valid
tBSDV
033
ns
J8
TCLK Low to Boundary Scan Output High Z
tBSDZ
033
ns
J9
TMS, TDI Input Data Setup Time to TCLK Rise
tTAPBST
4—
ns
J10
TMS, TDI Input Data Hold Time after TCLK Rise
tTAPBHT
10
ns
J11
TCLK Low to TDO Data Valid
tTDODV
026
ns
J12
TCLK Low to TDO High Z
tTDODZ
08
ns
J13
TRST Assert Time
tTRSTAT
100
ns
J14
TRST Setup Time (Negation) to TCLK High
tTRSTST
10
ns
QSPI_CS[3:0]
QSPI_CLK
QSPI_DOUT
QS5
QS1
QSPI_DIN
QS3
QS4
QS2
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MCF53721CVM240,
MCF5372LCVM240,
MCF5373LCVM240
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