MCF532x ColdFire Microprocessor Data Sheet, Rev. 5 Electrical Characteristics Fr" />
參數(shù)資料
型號: MCF53281CVM240J
廠商: Freescale Semiconductor
文件頁數(shù): 30/50頁
文件大?。?/td> 0K
描述: IC MPU RISC 240MHZ 256MAPBGA
標準包裝: 90
系列: MCF532x
核心處理器: Coldfire V3
芯體尺寸: 32-位
速度: 240MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,SPI,SSI,UART/USART,USB,USB OTG
外圍設備: DMA,LCD,PWM,WDT
輸入/輸出數(shù): 94
程序存儲器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Electrical Characteristics
Freescale Semiconductor
36
Table 22 lists specifications for the I2C output timing parameters shown in Figure 22.
Figure 22 shows timing for the values in Table 22 and Table 21.
Figure 22. I2C Input/Output Timings
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL =0.5 V)
1
ms
I6
Clock high time
4
tcyc
I7
Data setup time
0
ns
I8
Start condition setup time (for repeated start condition only)
2
tcyc
I9
Stop condition setup time
2
tcyc
Table 22. I2C Output Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I11
1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 22. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers
given in Table 22 are minimum values.
Start condition hold time
6
tcyc
I2 1
Clock low period
10
tcyc
I3 2
2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V)
s
I4 1
Data hold time
7
tcyc
I5 3
3 Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
3
ns
I6 1
Clock high time
10
tcyc
I7 1
Data setup time
2
tcyc
I8 1
Start condition setup time (for repeated start condition only)
20
tcyc
I9 1
Stop condition setup time
10
tcyc
Table 21. I2C Input Timing Specifications between SCL and SDA (continued)
Num
Characteristic
Min
Max
Units
I2
I6
I1
I4
I7
I8
I9
I5
I3
I2C_SCL
I2C_SDA
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