參數(shù)資料
型號(hào)： MCF5307FT66B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 66 MHz, RISC PROCESSOR, PQFP208
封裝： 28 X 28 MM, PLASTIC, QFP-208
文件頁(yè)數(shù)： 2/30頁(yè)
文件大?。?/td> 117K
代理商： MCF5307FT66B
10
MCF5307 Product Brief
MOTOROLA
System Interface, Continued
Interrupt Controller
The interrupt controller provides user-programmable control of 10 internal
peripheral interrupts and implements 4 external xed interrupt-request pins.
You can program each internal interrupt to any one of 7 interrupt levels and 4
priority levels within each of these levels and can program the external
interrupt request pins to level 1, 3, 5, and 7 or levels 2, 4, 6, and 7.
Autovector capability is available for internal and external interrupts.
JTAG
To help with system diagnostics and manufacturing testing, the MCF5307
processor includes dedicated user-accessible test logic that complies with the
IEEE 1149.1a standard for boundary-scan testability, often referred to as Joint
Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1a
standard.
System Debug Interface
The ColdFire processor core debug interface supports real-time trace and
debug, along with background debug mode (BDM). The BDM interface is
implemented using a serial communication channel with an emulator. The
BDM is compatible with the BDM interface provided on Motorola’s 683XX
Family of parts.
To support real-time trace, four output bits (PST) provide status information
on processor activity on a cycle-by-cycle basis. Additionally, a 4-bit output
data bus (DDATA) can be congured to display operand data and certain
change-of-ow target addresses for determining the dynamic execution path
through the application.
Finally, the Debug module provides a number of on-chip breakpoint registers
that can be congured by an emulator, or by the processor itself to generate
special debug interrupts or processor halts. The breakpoint resources include
two 32-bit address registers, a 32-bit PC and 32-bit PC mask registers, and a
32-bit data register and 32-bit data mask register. These breakpoint registers
can be congured in single- or double-level triggers where you dene the
trigger response.
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