參數(shù)資料
型號(hào): MCF5274CVM166
廠商: Freescale Semiconductor
文件頁數(shù): 38/44頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 166MHZ 256-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: MCF527x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 166MHz
連通性: EBI/EMI,以太網(wǎng),I²C,SPI,UART/USART,USB
外圍設(shè)備: DMA,WDT
輸入/輸出數(shù): 69
程序存儲(chǔ)器類型: ROMless
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 1.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
Documentation
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor
43
9
Documentation
Documentation regarding the MCF5275 and their development support tools is available from a local
Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center,
or through the Freescale web address at http://www.freescale.com/coldfire.
10
Revision History
Table 29 provides a revision history for this hardware specification.
Table 29. Document Revision History
Rev. No.
Substantive Change(s)
0
Initial release.
1
Added Figure 6.
1.1
Removed duplicate information in the module description sections. The information is all in the Signals
Description Table.
1.2
Removed Overview, Features, Signal Descriptions, Modes of Operation, and Address Multiplexing sections. This
information can be found in the MCF5275 Reference Manual.
Removed list of documentation in Section 9, “Documentation.”. An up-to-date list is always available on our web
site.
Changed CLKOUT -> PSTCLK in Section 8.16, “Debug AC Timing Specifications.”
Table 10: Update VDD spec from 1.35-1.65 to 1.4-1.6.
Table 13: Timings B6a, B6b, B6c, B7, B7a, B9, B12 updated:
B6a, B6b, B6c maximum changed from “0.5tCYC + 5” to “0.5tCYC +5.5”
B7, B7a minimum changed from “0.5tCYC + 1.5” to “0.5tCYC +1.0”
B9, B11 minimum changed from “1.5” to “1.0”
1.3
Added thermal characteristics for 196 MAPBGA in Table 8.
Updated package dimensions drawing, Figure 6.
2
FECn_TXEN, FECn_TXER, FECn_TXCLK),” regarding no minimum frequency requirement for TXCLK.
Removed third and fourth paragraphs from Section 8.11.2, “MII Transmit Signal Timing (FECn_TXD[3:0],
FECn_TXEN, FECn_TXER, FECn_TXCLK),” as this feature is not supported on this device.
3
Corrected Ordering Information, Table 6.
Figure 2: Moved PLLVDD from 1.5V to 3.3V supply line and corrected relevant text in sections below table.
Table 10: Corrected maximum “Input High Voltage 3.3V I/O Pads”, VIH specification.
4
Table 10, added PLL supply voltage row
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