MCF5271 Reference Manual, Rev. 2
Index-8
Freescale Semiconductor
output port command (UOP1n/UOP0n)
24-16 transmit buffers (UTBn)
24-12 Reset controller
registers
requests
signals
RNG
registers
output FIFO (RNGOUT)
27-4S
SCM
registers
bus master park (MPARK)
11-11core reset status (CRSR)
11-6core watchdog control (CWCR)
11-7core watchdog service (CWSR)
11-8grouped peripheral access control (GPACR)
11-17master privilege (MPR)
11-14peripheral access control (PACRn)
11-15 SDRAM controller
example
DACR initialization
18-21initialization code
18-25interface configuration
18-20synchronous
address multiplexing
18-9registers
address and control 0–1 (DACRn)
18-6 mode register
signals
Signals
CCM
chip select module
byte strobes (BS3–0)
16-2clock module
debug
debug data (DDATA3–0)
30-2development serial clock (DSCLK)
30-2development serial input (DSI)
30-2development serial output (DSO)
30-2processor status (PST3–0)
30-2JTAG
test data input/development serial input
test data output/development serial output
test mode select/breakpoint (TMS/BKPT
)29-4test reset/development serial clock
QSPI