參數(shù)資料
型號: MCF5251VM140
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 140 MHz, MICROPROCESSOR, PBGA225
封裝: LEAD FREE, MAPBGA-225
文件頁數(shù): 11/34頁
文件大?。?/td> 674K
代理商: MCF5251VM140
Package Information and Pinout
MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3
Freescale Semiconductor
19
5
Package Information and Pinout
This section includes the pin assignment information, contact connection diagram, and the mechanical
package drawing.
The MCF5251 device is available in the following package:
225 MAPBGA 13 x 13 mm 0.8 mm pitch package as shown in Figure 6.
5.1
Pin Assignment
Table 18 defines all the settings of each pad. See Figure 7 for the ball map of pin locations and Table 20
for the device pin list, sorted by signal identification.
Table 17. JTAG Timing Parameters
ID
Characteristic
Min
Max
Units
TCK Frequency of Operation
0
10
MHz
J1
TCK Cycle Time
100
ns
J2A
TCK Clock Pulse High Width
25
ns
J2B
TCK Clock Pulse Low Width
25
ns
J3A
TCK Fall Time (VIH=2.4 V to VIL=0.5 V)
5
ns
J3B
TCK Rise Time (VIL=0.5 v to VIH=2.4 V)
5
ns
J4
TDI, TMS to TCK rising (Input Setup)
8
ns
J5
TCK rising to TDI, TMS Invalid (Hold)
10
ns
J6
Boundary Scan Data Valid to TCK (Setup)
1
ns
J7
TCK to Boundary Scan Data Invalid to rising edge (Hold)
10
ns
J8
TRST Pulse Width (asynchronous to clock edges)
12
ns
J9
TCK falling to TDO Valid (signal from driven or three-state)
15
ns
J10
TCK falling to TDO High Impedance
2
15
ns
J11
TCK falling to Boundary Scan Data Valid (signal from driven or three-state)
15
ns
J12
TCK falling to Boundary Scan. Data High Impedance
1
15
ns
Table 18. 225 MAPBGA Pin Assignment
Name
Drive Type/
Strength
Load
(pF)
1st
Function
2nd
Function
Pinconfig
Register
Bit
GP
Pin
Reset
Notes
Address Bus
A1
O / 2 mA
30
––
X
H
3
A2
O / 2 mA
30
––
X
H
2
A3
O / 2 mA
30
––
X
H
1
A4
O / 2 mA
30
––
X
H
5
A5
O / 2 mA
30
––
X
G
1
A6
O / 2 mA
30
––
X
G
3
A7
O / 2 mA
30
––
X
G
2
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