參數(shù)資料
型號: MCF5251CVM140
廠商: Freescale Semiconductor
文件頁數(shù): 9/34頁
文件大小: 0K
描述: IC MPU 32BIT 140MHZ 225-MAPBGA
視頻文件: ColdFire MCF5251 Automotive Infotainment
標(biāo)準(zhǔn)包裝: 160
系列: MCF524x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 140MHz
連通性: ATA,音頻,CAN,EBI/EMI,I²C,IDE,MMC/SD,SPI,UART/USART,USB,OTG
外圍設(shè)備: DMA
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.08 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 225-LFBGA
包裝: 托盤
Electrical Specifications
MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3
Freescale Semiconductor
17
4.2
SPDIF Timing
The Sony/Philips Digital Interface (SPDIF) timing parameters are provided in Table 14. SPDIF timing is
totally asynchronous, therefore there is no need for relationship with the clock. Table 14 shows the
differences between high-low and low-high propagation delay which is called the skew.
4.3
Serial Audio Interface Timing
The Serial Audio Interface fully complies with the Industry standard Philips IIS (InterIC Serial Audio Bus)
timings.
4.4
DDATA/PST/PSTCLK Debug Interface
Table 15 provides the timing parameters.
Table 13. SDRAM Bus Timing Parameters
ID
Characteristic
Timing to 50% Points
Maximum
Units
30 pF
Load
40 pF
Load
50 pF
Load
D1
Propagation delay BCLK rising to data valid
7.88
8.8
9.6
ns
D2
Propagation delay BCLK rising to BCLKE, SDLDQM,
SDUDQM, SDWE, SDCS0, SDRAS, SDCAS valid
8.7
ns
D3
Propagation delay BCLK rising to A[24:9] valid
8.3
9.2
ns
D4
Set-up time data valid to BCLK rising
0
ns
D5
Hold time BCLK rising to data valid
0.7
ns
Table 14. SPDIF Propagation Skew and Transition Parameters
Characteristic
Pin Load
Prop Delay
Maximum
Skew1
Maximum
1 Skew value does not include the skew introduced by different rise and fall times.
Transition2 Rise
Maximum
2 Transition times between 10% Vdd and 90% Vdd.
Transition Fall
Maximum
Units
EBUIN1, EBUIN2, EBUIN3, EBUIN4:
asynchronous inputs, no specs apply
––
0.7
ns
EBUOUT1, EBUOUT2 output
40 pF
1.5
24.2
31.3
ns
EBUOUT1, EBUOUT2 output
20 pF
1.5
13.6
18.0
ns
Table 15. DDATA/PST/PSTCLK Debug Interface Timing Parameters
Characteristic
Pin Load
Min
Max
Units
PSTCLK clock rise edge to DDATA/PSTDATA1 invalid
15 pF
–1.0
ns
PSTCLK clock rise edge to DDATA/PSTDATA2 valid
15 pF
4.0
ns
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