
Electrical Specifications
MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3
16
Freescale Semiconductor
Table 12 shows the CRIN Crystal suggested parameters.
4.1
SDRAM Bus Timing
The SDRAM bus is a synchronous bus. Propagation delays, set-up times and hold times with respect to
the SDRAM clock BCLK are shown in
Figure 4 and the parameters provided in
Table 13. When BCLK
clock is not active, SDRAM interface is not valid and the external bus cannot be used.
Figure 4. SDRAM Bus Timing Diagram
Table 12. CRIN Crystal Suggested Parameters
Parameter
Min
Typ
Max
Unit
Frequency
5
–
16.94
MHz
Frequency Tolerance
–
±50
ppm
Frequency Stability Over Operating Temperature Range
–
±50
ppm
ESR
–40
–
Ω
Shunt Capacitance
–
7
–
pF
Load Capacitance
–
18
–
pF
BCLK
data (write)
BCLKE, SDXDQM, SDWE,
SDCS0, SDRAS, SDCAS
A[24:9]
data (read)
D1
D2
D3
D4
D5