參數(shù)資料
型號: MCF5251CDVM140
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 140 MHz, MICROPROCESSOR, PBGA225
封裝: LEAD FREE, MAPBGA-225
文件頁數(shù): 10/32頁
文件大?。?/td> 652K
代理商: MCF5251CDVM140
Package Information and Pinout
MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 2.1
18
Freescale Semiconductor
5
Package Information and Pinout
This section includes the pin assignment information, contact connection diagram, and the mechanical
package drawing.
The MCF5251 device is available in the following package:
225 MAPBGA 13 x 13 mm 0.8 mm pitch package as shown in Figure 5.
5.1
Pin Assignment
Table 16 defines all the settings of each pad. See Figure 6 for the ball map of pin locations and Table 18
for the device pin list, sorted by signal identification.
J11
TCK falling to Boundary Scan Data Valid (signal from driven or three-state)
15
ns
J12
TCK falling to Boundary Scan. Data High Impedance
1
15
ns
Table 16. 225 MAPBGA Pin Assignment
Name
Drive Type/
Strength
Load
(pF)
1st
Function
2nd
Function
Pinconfig
Register
Bit
GP
Pin
Reset
Notes
Address Bus
A1
O / 2 mA
30
––
X
H
3
A2
O / 2 mA
30
––
X
H
2
A3
O / 2 mA
30
––
X
H
1
A4
O / 2 mA
30
––
X
H
5
A5
O / 2 mA
30
––
X
G
1
A6
O / 2 mA
30
––
X
G
3
A7
O / 2 mA
30
––
X
G
2
A8
O / 2 mA
30
––
X
H
4
A9
O / 8 mA
30
––
X
H
6
A10
O / 8 mA
30
––
X
F
2
A11
O / 8 mA
30
––
X
G
5
A12
O / 8 mA
30
––
X
F
3
A13
O / 8 mA
30
––
X
F
1
A14
O / 8 mA
30
––
X
E
1
A15
O / 8 mA
30
––
X
G
4
A16
O / 8 mA
30
––
X
E
2
A17
O / 8 mA
30
––
X
F
4
A18
O / 8 mA
30
––
X
E
3
A19
O / 8 mA
30
––
X
F
5
A20/A24
O / 8 mA
30
A20
A24
31
X
F
6
Audio Clock Select: 1-LRCK3
pin; 0-CRIN pin
A21
O / 8 mA
30
––
X
D
3
A22
O / 8 mA
30
––
X
D
1
A23/GPO54
O / 8 mA
30
A23
––
O54
X
D
2
Boot Mode Select:1-Memory
connected to CS0; 0-Internal
boot rom
Table 15. JTAG Timing Parameters (continued)
ID
Characteristic
Min
Max
Units
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