參數(shù)資料
型號: MCF5235CVM100
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256
封裝: ROHS COMPLIANT, MAPBGA-256
文件頁數(shù): 31/48頁
文件大小: 666K
代理商: MCF5235CVM100
Electrical Characteristics
MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
Freescale Semiconductor
37
7.9
I2C Input/Output Timing Specifications
Table 16 lists specifications for the I2C input timing parameters shown in Figure 18.
Table 17 lists specifications for the I2C output timing parameters shown in Figure 18.
Figure 18 shows timing for the values in Table 16 and Table 17.
Table 16. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2
tcyc
I2
Clock low period
8
tcyc
I3
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
1
ms
I4
Data hold time
0
ns
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
1
ms
I6
Clock high time
4
tcyc
I7
Data setup time
0
ns
I8
Start condition setup time (for repeated start condition only)
2
tcyc
I9
Stop condition setup time
2
tcyc
Table 17. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I11
1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with
the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 17. The
I2C interface is designed to scale the actual data transition time to move it to the middle of the
I2C_SCL low period. The actual position is affected by the prescale and division values programmed
into the IFDR; however, the numbers given in Table 17 are minimum values.
Start condition hold time
6
tcyc
I2 1
Clock low period
10
tcyc
I3 2
2
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only
actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external
signal capacitance and pull-up resistor values.
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
s
I4 1
Data hold time
7
tcyc
I5 3
3
Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
3
ns
I6 1
Clock high time
10
tcyc
I7 1
Data setup time
2
tcyc
I8 1
Start condition setup time (for repeated start condition only)
20
tcyc
I9 1
Stop condition setup time
10
tcyc
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