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鏂囦欢闋佹暩(sh霉)锛� 14/55闋�
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MCF5223
5
ColdFire
Mic
roc
ontr
oller,
Re
v
.
1
0
F
reescale
Sem
ic
o
nductor
21
UART 13
UCTS1
SYNCA
URXD2
PUB[3]
PDSR[15]
鈥�
J3
24
16
URTS1
SYNCB
UTXD2
PUB[2]
PDSR[14]
鈥�
H3
23
15
URXD1
鈥�
FEC_TXD[0]
PUB[1]
PDSR[13]
PWOR[2]
鈥�
K3
32
23
UTXD1
鈥�
FEC_COL
PUB[0]
PDSR[12]
PWOR[3]
鈥�
L3
33
24
UART 2
UCTS2
鈥�
PUC[3]
PDSR[27]
鈥�
L10
61
鈥�
URTS2
鈥�
PUC[2]
PDSR[26]
鈥�
K10
60
鈥�
URXD2
鈥�
PUC[1]
PDSR[25]
鈥�
K11
62
鈥�
UTXD2
鈥�
PUC[0]
PDSR[24]
鈥�
L11
63
鈥�
FlexCAN
SYNCA
CANTX4
FEC_MDIO
PAS[3]
PDSR[39]
鈥�
28
20
SYNCB
CANRX4
FEC_MDC
PAS[2]
PDSR[39]
鈥�
27
19
VDD5,11
VDD
鈥�
N/A
鈥�
D7, E8
65,102
45,74
VDDX
鈥�
N/A
鈥�
D5, D6, E6, G5,
G6, G7, H6
14, 43
10, 31
VSS
鈥�
N/A
鈥�
E4, E5, E7,F4,
F5, F6, F7, F8
64,101
44,73
VSSX
鈥�
N/A
鈥�
15, 42
11, 30
1 The PDSR and PSSR registers are described in Chapter 14, 鈥淕eneral Purpose I/O Module. All programmable signals default to 2mA drive in normal
(single-chip) mode.
2 All signals have a pull-up in GPIO mode.
3 The use of an external PHY limits ADC, interrupt, and QSPI functionality. It also disables the UART0/1 and timer pins.
4 The multiplexed CANTX and CANRX signals do not have dedicated pins, but are available as muxed replacements for other signals.
5 The VDD1, VDD2, VDDPLL, and PHY_VDD pins are for decoupling only and should not have power directly applied to them.
6 For primary and GPIO functions only.
7 Only when JTAG mode is enabled.
8 For secondary and GPIO functions only.
9 RSTI has an internal pull-up resistor; however, the use of an external resistor is strongly recommended.
10 For GPIO function. Primary Function has pull-up control within the GPT module.
11 This list for power and ground does not include those dedicated power/ground pins included elsewhere, e.g. in the Ethernet PHY.
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group
Primary
Function
SecondaryF
unction
Tertiary
Function
Quaternary
Function
Drive
Strength/
Control1
Wired OR
Control
Pull-up/
Pull-down2
Pin on 121
MAPBGA
Pin on 112
LQFP
Pin on 80
LQFP
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鍙冩暩(sh霉)鎻忚堪
MCF52234 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:ColdFire Microcontroller
MCF52234CAL60 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU KIRIN2E EPP RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF52234CVM60 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU KIRIN2E 121 MAPBGA EPP RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF52234CVM60J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU MCU 32-Bit RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF52235 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:ColdFire Microcontroller